cleanup mmu interface

src/main/scala/vexriscv/Services.scala

@@ -68,24 +68,24 @@ case class MemoryTranslatorCmd() extends Bundle{
   val virtualAddress  = UInt(32 bits)
   val bypassTranslation = Bool
 }
-case class MemoryTranslatorRsp(wayCount : Int) extends Bundle{
+case class MemoryTranslatorRsp(p : MemoryTranslatorBusParameter) extends Bundle{
   val physicalAddress = UInt(32 bits)
   val isIoAccess = Bool
   val allowRead, allowWrite, allowExecute = Bool
   val exception = Bool
   val refilling = Bool
   val bypassTranslation = Bool
-  val ways = Vec(MemoryTranslatorRspWay(), wayCount)
+  val ways = Vec(MemoryTranslatorRspWay(), p.wayCount)
 }
 case class MemoryTranslatorRspWay() extends Bundle{
   val sel = Bool()
   val physical = UInt(32 bits)
 }
 
-
+case class MemoryTranslatorBusParameter(wayCount : Int)
-case class MemoryTranslatorBus(wayCount : Int) extends Bundle with IMasterSlave{
+case class MemoryTranslatorBus(p : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
   val cmd = MemoryTranslatorCmd()
-  val rsp = MemoryTranslatorRsp(wayCount)
+  val rsp = MemoryTranslatorRsp(p)
   val end = Bool
   val busy = Bool
 

src/main/scala/vexriscv/ip/DataCache.scala

@@ -125,13 +125,13 @@ case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
   val totalyConsistent = Bool() //Only for AMO/LRSC
 }
 
-case class DataCacheCpuMemory(p : DataCacheConfig, tlbWayCount : Int) extends Bundle with IMasterSlave{
+case class DataCacheCpuMemory(p : DataCacheConfig, mmu : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
   val isValid = Bool
   val isStuck = Bool
   val isRemoved = Bool
   val isWrite = Bool
   val address = UInt(p.addressWidth bit)
-  val mmuBus  = MemoryTranslatorBus(tlbWayCount)
+  val mmuBus  = MemoryTranslatorBus(mmu)
 
   override def asMaster(): Unit = {
     out(isValid, isStuck, isRemoved, address)
@@ -175,9 +175,9 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
   }
 }
 
-case class DataCacheCpuBus(p : DataCacheConfig, tlbWayCount : Int) extends Bundle with IMasterSlave{
+case class DataCacheCpuBus(p : DataCacheConfig, mmu : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
   val execute   = DataCacheCpuExecute(p)
-  val memory    = DataCacheCpuMemory(p, tlbWayCount)
+  val memory    = DataCacheCpuMemory(p, mmu)
   val writeBack = DataCacheCpuWriteBack(p)
 
   val redo = Bool()
@@ -423,11 +423,11 @@ object DataCacheExternalAmoStates extends SpinalEnum{
 }
 
 //If external amo, mem rsp should stay
-class DataCache(val p : DataCacheConfig, tlbWayCount : Int) extends Component{
+class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParameter) extends Component{
   import p._
 
   val io = new Bundle{
-    val cpu = slave(DataCacheCpuBus(p, tlbWayCount))
+    val cpu = slave(DataCacheCpuBus(p, mmuParameter))
     val mem = master(DataCacheMemBus(p))
   }
 

src/main/scala/vexriscv/ip/InstructionCache.scala

@@ -104,7 +104,7 @@ trait InstructionCacheCommons{
   val cacheMiss, error,  mmuRefilling, mmuException, isUser : Bool
 }
 
-case class InstructionCacheCpuFetch(p : InstructionCacheConfig, tlbWayCount : Int) extends Bundle with IMasterSlave with InstructionCacheCommons {
+case class InstructionCacheCpuFetch(p : InstructionCacheConfig, mmuParameter : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave with InstructionCacheCommons {
   val isValid = Bool()
   val isStuck = Bool()
   val isRemoved = Bool()
@@ -112,7 +112,7 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig, tlbWayCount : In
   val data = Bits(p.cpuDataWidth bits)
   val dataBypassValid = p.bypassGen generate Bool()
   val dataBypass = p.bypassGen generate Bits(p.cpuDataWidth bits)
-  val mmuBus  = MemoryTranslatorBus(tlbWayCount)
+  val mmuBus  = MemoryTranslatorBus(mmuParameter)
   val physicalAddress = UInt(p.addressWidth bits)
   val cacheMiss, error, mmuRefilling, mmuException, isUser  = ifGen(!p.twoCycleCache)(Bool)
   val haltIt  = Bool() //Used to wait on the MMU rsp busy
@@ -141,9 +141,9 @@ case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle
   }
 }
 
-case class InstructionCacheCpuBus(p : InstructionCacheConfig, tlbWayCount : Int) extends Bundle with IMasterSlave{
+case class InstructionCacheCpuBus(p : InstructionCacheConfig, mmuParameter : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
   val prefetch = InstructionCacheCpuPrefetch(p)
-  val fetch = InstructionCacheCpuFetch(p, tlbWayCount)
+  val fetch = InstructionCacheCpuFetch(p, mmuParameter)
   val decode = InstructionCacheCpuDecode(p)
   val fill = Flow(UInt(p.addressWidth bits))
 
@@ -277,11 +277,11 @@ case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{
   }
 }
 
-class InstructionCache(p : InstructionCacheConfig, tlbWayCount : Int) extends Component{
+class InstructionCache(p : InstructionCacheConfig, mmuParameter : MemoryTranslatorBusParameter) extends Component{
   import p._
   val io = new Bundle{
     val flush = in Bool()
-    val cpu = slave(InstructionCacheCpuBus(p, tlbWayCount))
+    val cpu = slave(InstructionCacheCpuBus(p, mmuParameter))
     val mem = master(InstructionCacheMemBus(p))
   }
 

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -175,7 +175,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       this.config.copy(
         mergeExecuteMemory = writeBack == null
       ),
-      tlbWayCount = mmuBus.rsp.wayCount
+      mmuParameter = mmuBus.p
     )
 
     //Interconnect the plugin dBus with the cache dBus with some optional pipelining

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -392,7 +392,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
     import pipeline._
     import pipeline.config._
 
-    object MMU_RSP extends Stageable(MemoryTranslatorRsp(mmuBus.rsp.wayCount))
+    object MMU_RSP extends Stageable(MemoryTranslatorRsp(mmuBus.p))
 
     dBus = master(DBusSimpleBus()).setName("dBus")
 

src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala

@@ -124,7 +124,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
     import pipeline.config._
 
     pipeline plug new FetchArea(pipeline) {
-      val cache = new InstructionCache(IBusCachedPlugin.this.config.copy(bypassGen = tightlyGen), mmuBus.rsp.wayCount)
+      val cache = new InstructionCache(IBusCachedPlugin.this.config.copy(bypassGen = tightlyGen), mmuBus.p)
       iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
       iBus <> cache.io.mem
       iBus.cmd.address.allowOverride := cache.io.mem.cmd.address

src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala

@@ -23,7 +23,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
 
   override def newTranslationPort(priority : Int,args : Any): MemoryTranslatorBus = {
     val config = args.asInstanceOf[MemoryTranslatorPortConfig]
-    val port = MemoryTranslatorPort(MemoryTranslatorBus(0),priority, config/*,exceptionBus*/)
+    val port = MemoryTranslatorPort(MemoryTranslatorBus(MemoryTranslatorBusParameter(wayCount = 0)),priority, config/*,exceptionBus*/)
     portsInfo += port
     port.bus
   }

src/main/scala/vexriscv/plugin/MmuPlugin.scala

@@ -48,7 +48,7 @@ class MmuPlugin(ioRange : UInt => Bool,
 
   override def newTranslationPort(priority : Int,args : Any): MemoryTranslatorBus = {
     val config = args.asInstanceOf[MmuPortConfig]
-    val port = MmuPort(MemoryTranslatorBus(config.portTlbSize),priority, config, portsInfo.length)
+    val port = MmuPort(MemoryTranslatorBus(MemoryTranslatorBusParameter(wayCount = config.portTlbSize)),priority, config, portsInfo.length)
     portsInfo += port
     port.bus
   }

src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala

@@ -11,7 +11,7 @@ class StaticMemoryTranslatorPlugin(ioRange : UInt => Bool) extends Plugin[VexRis
   val portsInfo = ArrayBuffer[StaticMemoryTranslatorPort]()
 
   override def newTranslationPort(priority : Int,args : Any): MemoryTranslatorBus = {
-    val port = StaticMemoryTranslatorPort(MemoryTranslatorBus(0),priority)
+    val port = StaticMemoryTranslatorPort(MemoryTranslatorBus(MemoryTranslatorBusParameter(wayCount = 0)),priority)
     portsInfo += port
     port.bus
   }