mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
Initial commit of PMP plugin
This commit is contained in:
Samuel Lindemer
parent
d490f903ea
commit
fc2c8a7c37
3 changed files with 292 additions and 0 deletions
85
src/main/scala/vexriscv/demo/GenZephyr.scala
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85
src/main/scala/vexriscv/demo/GenZephyr.scala
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@ -0,0 +1,85 @@
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package vexriscv.demo
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import vexriscv.plugin._
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
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import spinal.core._
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object GenZephyr extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new IBusCachedPlugin(
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prediction = STATIC,
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = true,
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twoCycleCache = true
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true
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)
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),
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new PmpPlugin(
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regions = 16,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrelShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulDivIterativePlugin(
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genMul = true,
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genDiv = true,
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mulUnrollFactor = 1,
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divUnrollFactor = 1
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),
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new CsrPlugin(CsrPluginConfig.zephyr(0x00000020l)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -264,6 +264,31 @@ object CsrPluginConfig{
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uinstretAccess = CsrAccess.NONE
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)
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def zephyr(mtvecInit : BigInt) = CsrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = 1,
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marchid = 2,
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mimpid = 3,
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mhartid = 0,
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misaExtensionsInit = 0,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = mtvecInit,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = true,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ucycleAccess = CsrAccess.NONE,
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uinstretAccess = CsrAccess.NONE,
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wfiGenAsWait = true,
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ecallGen = true,
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userGen = true,
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medelegAccess = CsrAccess.READ_WRITE,
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midelegAccess = CsrAccess.READ_WRITE
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)
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}
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case class CsrWrite(that : Data, bitOffset : Int)
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case class CsrRead(that : Data , bitOffset : Int)
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182
src/main/scala/vexriscv/plugin/PmpPlugin.scala
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182
src/main/scala/vexriscv/plugin/PmpPlugin.scala
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@ -0,0 +1,182 @@
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/*
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* Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se>
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*
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* SPDX-License-Identifier: MIT
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*/
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package vexriscv.plugin
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import vexriscv.{VexRiscv, _}
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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/* Each 32-bit pmpcfg# register contains four 8-bit configuration sections.
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* These section numbers contain flags which apply to region defined by the
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* corresponding pmpaddr# register.
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | pmp3cfg | pmp2cfg | pmp1cfg | pmp0cfg | pmpcfg0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | pmp7cfg | pmp6cfg | pmp5cfg | pmp4cfg | pmpcfg2
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 7 6 5 4 3 2 1 0
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | L | 0 | A | X | W | R | pmp#cfg
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* L: locks configuration until system reset (including M-mode)
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* 0: hardwired to zero
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* A: 0 = OFF (null region / disabled)
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* 1 = TOR (top of range)
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* 2 = NA4 (naturally aligned four-byte region)
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* 3 = NAPOT (naturally aligned power-of-two region, > 7 bytes)
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* X: execute
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* W: write
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* R: read
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*
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* TOR: Each 32-bit pmpaddr# register defines the upper bound of the pmp region
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* right-shifted by two bits. The lower bound of the region is the previous
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* pmpaddr# register. In the case of pmpaddr0, the lower bound is address 0x0.
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | address[33:2] | pmpaddr#
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* NAPOT: Each 32-bit pmpaddr# register defines the regionStart address and the size
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* of the pmp region. The number of concurrent 1s begging at the LSB indicates
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* the size of the region as a power of two (e.g. 0x...0 = 8-byte, 0x...1 =
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* 16-byte, 0x...11 = 32-byte, etc.).
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | address[33:2] |0|1|1|1|1| pmpaddr#
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* NA4: This is essentially an edge case of NAPOT where the entire pmpaddr#
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* register defines a 4-byte wide region.
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*/
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case class PmpRegister() extends Bundle {
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// CSR segments
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val x, w, r = Reg(Bool)
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val l = Reg(Bool) init(False)
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val a = Reg(UInt(2 bits)) init(0)
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val address = Reg(UInt(32 bits))
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// Computed region bounds
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val regionStart = UInt(32 bits)
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val regionEnd = UInt(32 bits)
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val valid = Bool
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// Addressing options
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def NA4 = 2
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def NAPOT = 3
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switch(a) {
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is(NA4) {
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regionStart := address |<< 2
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regionEnd := regionStart + 4
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valid := True
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}
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is(NAPOT) {
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val mask = address & ~(address + 1)
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regionStart := (address & ~mask) |<< 2
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regionEnd := regionStart + ((mask + 1) |<< 3)
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valid := True
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}
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default {
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regionStart := 0
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regionEnd := 0
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valid := False
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}
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}
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}
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case class ProtectedMemoryTranslatorPort(bus : MemoryTranslatorBus)
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class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator {
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// Each pmpcfg# CSR configures four regions.
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assert((regions % 4) == 0)
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val pmps = ArrayBuffer[PmpRegister]()
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val portsInfo = ArrayBuffer[ProtectedMemoryTranslatorPort]()
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override def newTranslationPort(priority : Int, args : Any): MemoryTranslatorBus = {
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val port = ProtectedMemoryTranslatorPort(MemoryTranslatorBus())
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portsInfo += port
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port.bus
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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import Riscv._
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val csrService = pipeline.service(classOf[CsrInterface])
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val privilegeService = pipeline.service(classOf[PrivilegeService])
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val core = pipeline plug new Area {
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// Instantiate pmpaddr0 ... pmpaddr# CSRs.
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for (n <- 0 until regions) {
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pmps += PmpRegister()
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csrService.rw(0x3B0 + n, pmps(n).address)
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}
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// Instantiate pmpcfg0 ... pmpcfg# CSRs.
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for (n <- 0 until (regions / 4)) {
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csrService.rw(0x3A0 + n,
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31 -> pmps((n * 4) + 3).l, 27 -> pmps((n * 4) + 3).a,
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26 -> pmps((n * 4) + 3).x, 25 -> pmps((n * 4) + 3).w, 24 -> pmps((n * 4) + 3).r,
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23 -> pmps((n * 4) + 2).l, 19 -> pmps((n * 4) + 2).a,
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18 -> pmps((n * 4) + 2).x, 17 -> pmps((n * 4) + 2).w, 16 -> pmps((n * 4) + 2).r,
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15 -> pmps((n * 4) + 1).l, 11 -> pmps((n * 4) + 1).a,
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10 -> pmps((n * 4) + 1).x, 9 -> pmps((n * 4) + 1).w, 8 -> pmps((n * 4) + 1).r,
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7 -> pmps((n * 4) ).l, 3 -> pmps((n * 4) ).a,
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2 -> pmps((n * 4) ).x, 1 -> pmps((n * 4) ).w, 0 -> pmps((n * 4) ).r
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)
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}
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// Connect memory ports to PMP logic.
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val ports = for ((port, portId) <- portsInfo.zipWithIndex) yield new Area {
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val address = port.bus.cmd.virtualAddress
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port.bus.rsp.physicalAddress := address
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// Only the first matching PMP region is applied.
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val hits = pmps.map(pmp => pmp.valid &&
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pmp.regionStart <= address &&
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pmp.regionEnd > address &&
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(pmp.l || ~privilegeService.isMachine()))
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// M-mode has full access by default. All others have none by default.
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when(CountOne(hits) === 0) {
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port.bus.rsp.allowRead := privilegeService.isMachine()
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port.bus.rsp.allowWrite := privilegeService.isMachine()
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port.bus.rsp.allowExecute := privilegeService.isMachine()
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} otherwise {
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port.bus.rsp.allowRead := MuxOH(OHMasking.first(hits), pmps).r
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port.bus.rsp.allowWrite := MuxOH(OHMasking.first(hits), pmps).w
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port.bus.rsp.allowExecute := MuxOH(OHMasking.first(hits), pmps).x
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}
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port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
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port.bus.rsp.exception := False
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port.bus.rsp.refilling := False
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port.bus.busy := False
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}
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}
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}
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}
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