#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.

This commit is contained in:
Charles Papon 2019-04-08 13:20:56 +02:00
parent c2595273ec
commit fd15a938c5
4 changed files with 250 additions and 234 deletions

View file

@ -6,13 +6,13 @@ Disassembly of section .init:
80000000 <_start>:
80000000: 00001117 auipc sp,0x1
80000004: 11010113 addi sp,sp,272 # 80001110 <_sp>
80000004: 11810113 addi sp,sp,280 # 80001118 <_sp>
80000008: 00001517 auipc a0,0x1
8000000c: 86850513 addi a0,a0,-1944 # 80000870 <__init_array_end>
8000000c: 87050513 addi a0,a0,-1936 # 80000878 <__init_array_end>
80000010: 00001597 auipc a1,0x1
80000014: 86058593 addi a1,a1,-1952 # 80000870 <__init_array_end>
80000014: 86858593 addi a1,a1,-1944 # 80000878 <__init_array_end>
80000018: 00001617 auipc a2,0x1
8000001c: 8f860613 addi a2,a2,-1800 # 80000910 <__bss_start>
8000001c: 90060613 addi a2,a2,-1792 # 80000918 <__bss_start>
80000020: 00c5fc63 bgeu a1,a2,80000038 <_start+0x38>
80000024: 00052283 lw t0,0(a0)
80000028: 0055a023 sw t0,0(a1)
@ -20,14 +20,14 @@ Disassembly of section .init:
80000030: 00458593 addi a1,a1,4
80000034: fec5e8e3 bltu a1,a2,80000024 <_start+0x24>
80000038: 00001517 auipc a0,0x1
8000003c: 8d850513 addi a0,a0,-1832 # 80000910 <__bss_start>
8000003c: 8e050513 addi a0,a0,-1824 # 80000918 <__bss_start>
80000040: 00001597 auipc a1,0x1
80000044: 8d058593 addi a1,a1,-1840 # 80000910 <__bss_start>
80000044: 8d858593 addi a1,a1,-1832 # 80000918 <__bss_start>
80000048: 00b57863 bgeu a0,a1,80000058 <_start+0x58>
8000004c: 00052023 sw zero,0(a0)
80000050: 00450513 addi a0,a0,4
80000054: feb56ce3 bltu a0,a1,8000004c <_start+0x4c>
80000058: 770000ef jal ra,800007c8 <__libc_init_array>
80000058: 778000ef jal ra,800007d0 <__libc_init_array>
8000005c: 17c000ef jal ra,800001d8 <init>
80000060: 00000097 auipc ra,0x0
80000064: 01408093 addi ra,ra,20 # 80000074 <done>
@ -117,7 +117,7 @@ Disassembly of section .text:
8000018c: 00054503 lbu a0,0(a0)
80000190: 00050a63 beqz a0,800001a4 <putString+0x28>
80000194: 00140413 addi s0,s0,1
80000198: 5f4000ef jal ra,8000078c <putC>
80000198: 5fc000ef jal ra,80000794 <putC>
8000019c: 00044503 lbu a0,0(s0)
800001a0: fe051ae3 bnez a0,80000194 <putString+0x18>
800001a4: 00c12083 lw ra,12(sp)
@ -149,18 +149,18 @@ Disassembly of section .text:
800001fc: 3a079073 csrw pmpcfg0,a5
80000200: 30529073 csrw mtvec,t0
80000204: 80001437 lui s0,0x80001
80000208: 5bc000ef jal ra,800007c4 <halInit>
8000020c: 8e440413 addi s0,s0,-1820 # 800008e4 <_sp+0xfffff7d4>
80000208: 5c4000ef jal ra,800007cc <halInit>
8000020c: 8ec40413 addi s0,s0,-1812 # 800008ec <_sp+0xfffff7d4>
80000210: 02a00513 li a0,42
80000214: 00140413 addi s0,s0,1
80000218: 574000ef jal ra,8000078c <putC>
80000218: 57c000ef jal ra,80000794 <putC>
8000021c: 00044503 lbu a0,0(s0)
80000220: fe051ae3 bnez a0,80000214 <init+0x3c>
80000224: 800007b7 lui a5,0x80000
80000228: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
80000228: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef64>
8000022c: 30579073 csrw mtvec,a5
80000230: 800017b7 lui a5,0x80001
80000234: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
80000234: 09878793 addi a5,a5,152 # 80001098 <_sp+0xffffff80>
80000238: 34079073 csrw mscratch,a5
8000023c: 000017b7 lui a5,0x1
80000240: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
@ -175,10 +175,10 @@ Disassembly of section .text:
80000264: 30379073 csrw mideleg,a5
80000268: 14305073 csrwi stval,0
8000026c: 80001437 lui s0,0x80001
80000270: 8fc40413 addi s0,s0,-1796 # 800008fc <_sp+0xfffff7ec>
80000270: 90440413 addi s0,s0,-1788 # 80000904 <_sp+0xfffff7ec>
80000274: 02a00513 li a0,42
80000278: 00140413 addi s0,s0,1
8000027c: 510000ef jal ra,8000078c <putC>
8000027c: 518000ef jal ra,80000794 <putC>
80000280: 00044503 lbu a0,0(s0)
80000284: fe051ae3 bnez a0,80000278 <init+0xa0>
80000288: 00c12083 lw ra,12(sp)
@ -188,7 +188,7 @@ Disassembly of section .text:
80000298 <readRegister>:
80000298: 800017b7 lui a5,0x80001
8000029c: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
8000029c: 09878793 addi a5,a5,152 # 80001098 <_sp+0xffffff80>
800002a0: 00251513 slli a0,a0,0x2
800002a4: 00f50533 add a0,a0,a5
800002a8: 00052503 lw a0,0(a0)
@ -197,7 +197,7 @@ Disassembly of section .text:
800002b0 <writeRegister>:
800002b0: 800017b7 lui a5,0x80001
800002b4: 00251513 slli a0,a0,0x2
800002b8: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
800002b8: 09878793 addi a5,a5,152 # 80001098 <_sp+0xffffff80>
800002bc: 00f50533 add a0,a0,a5
800002c0: 00b52023 sw a1,0(a0)
800002c4: 00008067 ret
@ -205,7 +205,7 @@ Disassembly of section .text:
800002c8 <redirectTrap>:
800002c8: ff010113 addi sp,sp,-16
800002cc: 00112623 sw ra,12(sp)
800002d0: 4b4000ef jal ra,80000784 <stopSim>
800002d0: 4bc000ef jal ra,8000078c <stopSim>
800002d4: 343027f3 csrr a5,mtval
800002d8: 14379073 csrw stval,a5
800002dc: 341027f3 csrr a5,mepc
@ -220,7 +220,7 @@ Disassembly of section .text:
80000300 <emulationTrapToSupervisorTrap>:
80000300: 800007b7 lui a5,0x80000
80000304: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
80000304: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef64>
80000308: 30579073 csrw mtvec,a5
8000030c: 343027f3 csrr a5,mtval
80000310: 14379073 csrw stval,a5
@ -254,7 +254,7 @@ Disassembly of section .text:
80000378: 00020737 lui a4,0x20
8000037c: 30073073 csrc mstatus,a4
80000380: 00068513 mv a0,a3
80000384: 00f5a023 sw a5,0(a1) # c3000000 <_sp+0x42ffeef0>
80000384: 00f5a023 sw a5,0(a1) # c3000000 <_sp+0x42ffeee8>
80000388: 00008067 ret
8000038c <writeWord>:
@ -285,7 +285,7 @@ Disassembly of section .text:
800003e4: 00900693 li a3,9
800003e8: 04d79463 bne a5,a3,80000430 <trap+0x74>
800003ec: 80001437 lui s0,0x80001
800003f0: 11040413 addi s0,s0,272 # 80001110 <_sp+0x0>
800003f0: 11840413 addi s0,s0,280 # 80001118 <_sp+0x0>
800003f4: fc442783 lw a5,-60(s0)
800003f8: 00100693 li a3,1
800003fc: fa842503 lw a0,-88(s0)
@ -298,10 +298,10 @@ Disassembly of section .text:
80000418: 01012903 lw s2,16(sp)
8000041c: 00c12983 lw s3,12(sp)
80000420: 02010113 addi sp,sp,32
80000424: 3600006f j 80000784 <stopSim>
80000424: 3680006f j 8000078c <stopSim>
80000428: 00777713 andi a4,a4,7
8000042c: 14f70063 beq a4,a5,8000056c <trap+0x1b0>
80000430: 354000ef jal ra,80000784 <stopSim>
80000430: 35c000ef jal ra,8000078c <stopSim>
80000434: 343027f3 csrr a5,mtval
80000438: 14379073 csrw stval,a5
8000043c: 341027f3 csrr a5,mepc
@ -346,7 +346,7 @@ Disassembly of section .text:
800004d8: 10f70c63 beq a4,a5,800005f0 <trap+0x234>
800004dc: 00100993 li s3,1
800004e0: 03370463 beq a4,s3,80000508 <trap+0x14c>
800004e4: 2a0000ef jal ra,80000784 <stopSim>
800004e4: 2a8000ef jal ra,8000078c <stopSim>
800004e8: 343027f3 csrr a5,mtval
800004ec: 14379073 csrw stval,a5
800004f0: 341027f3 csrr a5,mepc
@ -361,7 +361,7 @@ Disassembly of section .text:
80000514: 0ed70663 beq a4,a3,80000600 <trap+0x244>
80000518: c8178793 addi a5,a5,-895
8000051c: 0cf70463 beq a4,a5,800005e4 <trap+0x228>
80000520: 264000ef jal ra,80000784 <stopSim>
80000520: 26c000ef jal ra,8000078c <stopSim>
80000524: 343027f3 csrr a5,mtval
80000528: 14379073 csrw stval,a5
8000052c: 341027f3 csrr a5,mepc
@ -373,7 +373,7 @@ Disassembly of section .text:
80000544: 1c099063 bnez s3,80000704 <trap+0x348>
80000548: 00545413 srli s0,s0,0x5
8000054c: 800017b7 lui a5,0x80001
80000550: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
80000550: 09878793 addi a5,a5,152 # 80001098 <_sp+0xffffff80>
80000554: 07c47413 andi s0,s0,124
80000558: 00f40433 add s0,s0,a5
8000055c: 01242023 sw s2,0(s0)
@ -383,7 +383,7 @@ Disassembly of section .text:
8000056c: 00d45713 srli a4,s0,0xd
80000570: 01245793 srli a5,s0,0x12
80000574: 800016b7 lui a3,0x80001
80000578: 09068693 addi a3,a3,144 # 80001090 <_sp+0xffffff80>
80000578: 09868693 addi a3,a3,152 # 80001098 <_sp+0xffffff80>
8000057c: 07c77713 andi a4,a4,124
80000580: 07c7f793 andi a5,a5,124
80000584: 00d70733 add a4,a4,a3
@ -406,42 +406,42 @@ Disassembly of section .text:
800005c8: e6f564e3 bltu a0,a5,80000430 <trap+0x74>
800005cc: 80001537 lui a0,0x80001
800005d0: 00279793 slli a5,a5,0x2
800005d4: 87050513 addi a0,a0,-1936 # 80000870 <_sp+0xfffff760>
800005d4: 87850513 addi a0,a0,-1928 # 80000878 <_sp+0xfffff760>
800005d8: 00a787b3 add a5,a5,a0
800005dc: 0007a783 lw a5,0(a5)
800005e0: 00078067 jr a5
800005e4: 1c0000ef jal ra,800007a4 <rdtimeh>
800005e4: 1c8000ef jal ra,800007ac <rdtimeh>
800005e8: 00050913 mv s2,a0
800005ec: f59ff06f j 80000544 <trap+0x188>
800005f0: 00f45993 srli s3,s0,0xf
800005f4: 01f9f993 andi s3,s3,31
800005f8: 013039b3 snez s3,s3
800005fc: f0dff06f j 80000508 <trap+0x14c>
80000600: 19c000ef jal ra,8000079c <rdtime>
80000600: 1a4000ef jal ra,800007a4 <rdtime>
80000604: 00050913 mv s2,a0
80000608: f3dff06f j 80000544 <trap+0x188>
8000060c: 01067463 bgeu a2,a6,80000614 <trap+0x258>
80000610: 00080613 mv a2,a6
80000614: 00545413 srli s0,s0,0x5
80000618: 07c47413 andi s0,s0,124
8000061c: 00d406b3 add a3,s0,a3
80000620: 0106a023 sw a6,0(a3)
80000624: 000207b7 lui a5,0x20
80000628: 3007a073 csrs mstatus,a5
8000062c: 00000797 auipc a5,0x0
80000630: 01878793 addi a5,a5,24 # 80000644 <trap+0x288>
80000634: 30579073 csrw mtvec,a5
80000638: 00100693 li a3,1
8000063c: 00c72023 sw a2,0(a4)
80000640: 00000693 li a3,0
80000644: 000207b7 lui a5,0x20
80000648: 3007b073 csrc mstatus,a5
8000064c: 800007b7 lui a5,0x80000
80000650: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
80000654: 0e069063 bnez a3,80000734 <trap+0x378>
80000614: 00020537 lui a0,0x20
80000618: 30052073 csrs mstatus,a0
8000061c: 00000517 auipc a0,0x0
80000620: 01850513 addi a0,a0,24 # 80000634 <trap+0x278>
80000624: 30551073 csrw mtvec,a0
80000628: 00100793 li a5,1
8000062c: 00c72023 sw a2,0(a4)
80000630: 00000793 li a5,0
80000634: 00020537 lui a0,0x20
80000638: 30053073 csrc mstatus,a0
8000063c: 80000737 lui a4,0x80000
80000640: 07c70713 addi a4,a4,124 # 8000007c <_sp+0xffffef64>
80000644: 14079063 bnez a5,80000784 <trap+0x3c8>
80000648: 00545793 srli a5,s0,0x5
8000064c: 07c7f793 andi a5,a5,124
80000650: 00d786b3 add a3,a5,a3
80000654: 0106a023 sw a6,0(a3)
80000658: 00448493 addi s1,s1,4
8000065c: 34149073 csrw mepc,s1
80000660: 30579073 csrw mtvec,a5
80000660: 30571073 csrw mtvec,a4
80000664: df1ff06f j 80000454 <trap+0x98>
80000668: 01064633 xor a2,a2,a6
8000066c: fa9ff06f j 80000614 <trap+0x258>
@ -460,14 +460,14 @@ Disassembly of section .text:
800006a0: f6c85ae3 bge a6,a2,80000614 <trap+0x258>
800006a4: 00080613 mv a2,a6
800006a8: f6dff06f j 80000614 <trap+0x258>
800006ac: 0e8000ef jal ra,80000794 <getC>
800006ac: 0f0000ef jal ra,8000079c <getC>
800006b0: faa42423 sw a0,-88(s0)
800006b4: 341027f3 csrr a5,mepc
800006b8: 00478793 addi a5,a5,4
800006bc: 34179073 csrw mepc,a5
800006c0: d95ff06f j 80000454 <trap+0x98>
800006c4: fac42583 lw a1,-84(s0)
800006c8: 0e4000ef jal ra,800007ac <setMachineTimerCmp>
800006c8: 0ec000ef jal ra,800007b4 <setMachineTimerCmp>
800006cc: 08000793 li a5,128
800006d0: 3047a073 csrs mie,a5
800006d4: 02000793 li a5,32
@ -477,12 +477,12 @@ Disassembly of section .text:
800006e4: 34179073 csrw mepc,a5
800006e8: d6dff06f j 80000454 <trap+0x98>
800006ec: 0ff57513 andi a0,a0,255
800006f0: 09c000ef jal ra,8000078c <putC>
800006f0: 0a4000ef jal ra,80000794 <putC>
800006f4: 341027f3 csrr a5,mepc
800006f8: 00478793 addi a5,a5,4
800006fc: 34179073 csrw mepc,a5
80000700: d55ff06f j 80000454 <trap+0x98>
80000704: 080000ef jal ra,80000784 <stopSim>
80000704: 088000ef jal ra,8000078c <stopSim>
80000708: 343027f3 csrr a5,mtval
8000070c: 14379073 csrw stval,a5
80000710: 341027f3 csrr a5,mepc
@ -493,7 +493,7 @@ Disassembly of section .text:
80000724: 34179073 csrw mepc,a5
80000728: e21ff06f j 80000548 <trap+0x18c>
8000072c: 800007b7 lui a5,0x80000
80000730: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
80000730: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef64>
80000734: 30579073 csrw mtvec,a5
80000738: 343027f3 csrr a5,mtval
8000073c: 14379073 csrw stval,a5
@ -514,78 +514,80 @@ Disassembly of section .text:
80000778: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
8000077c: 3007a073 csrs mstatus,a5
80000780: cd5ff06f j 80000454 <trap+0x98>
80000784: 30571073 csrw mtvec,a4
80000788: fb1ff06f j 80000738 <trap+0x37c>
80000784 <stopSim>:
80000784: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7fffeeec>
80000788: 0000006f j 80000788 <stopSim+0x4>
8000078c <stopSim>:
8000078c: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7fffeee4>
80000790: 0000006f j 80000790 <stopSim+0x4>
8000078c <putC>:
8000078c: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7fffeee8>
80000790: 00008067 ret
80000794 <getC>:
80000794: ff802503 lw a0,-8(zero) # fffffff8 <_sp+0x7fffeee8>
80000794 <putC>:
80000794: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7fffeee0>
80000798: 00008067 ret
8000079c <rdtime>:
8000079c: fe002503 lw a0,-32(zero) # ffffffe0 <_sp+0x7fffeed0>
8000079c <getC>:
8000079c: ff802503 lw a0,-8(zero) # fffffff8 <_sp+0x7fffeee0>
800007a0: 00008067 ret
800007a4 <rdtimeh>:
800007a4: fe402503 lw a0,-28(zero) # ffffffe4 <_sp+0x7fffeed4>
800007a4 <rdtime>:
800007a4: fe002503 lw a0,-32(zero) # ffffffe0 <_sp+0x7fffeec8>
800007a8: 00008067 ret
800007ac <setMachineTimerCmp>:
800007ac: fec00793 li a5,-20
800007b0: fff00713 li a4,-1
800007b4: 00e7a023 sw a4,0(a5)
800007b8: fea02423 sw a0,-24(zero) # ffffffe8 <_sp+0x7fffeed8>
800007bc: 00b7a023 sw a1,0(a5)
800007c0: 00008067 ret
800007ac <rdtimeh>:
800007ac: fe402503 lw a0,-28(zero) # ffffffe4 <_sp+0x7fffeecc>
800007b0: 00008067 ret
800007c4 <halInit>:
800007c4: 00008067 ret
800007b4 <setMachineTimerCmp>:
800007b4: fec00793 li a5,-20
800007b8: fff00713 li a4,-1
800007bc: 00e7a023 sw a4,0(a5)
800007c0: fea02423 sw a0,-24(zero) # ffffffe8 <_sp+0x7fffeed0>
800007c4: 00b7a023 sw a1,0(a5)
800007c8: 00008067 ret
800007c8 <__libc_init_array>:
800007c8: ff010113 addi sp,sp,-16
800007cc: 00000797 auipc a5,0x0
800007d0: 0a478793 addi a5,a5,164 # 80000870 <__init_array_end>
800007d4: 00812423 sw s0,8(sp)
800007d8: 00000417 auipc s0,0x0
800007dc: 09840413 addi s0,s0,152 # 80000870 <__init_array_end>
800007e0: 40f40433 sub s0,s0,a5
800007e4: 00912223 sw s1,4(sp)
800007e8: 01212023 sw s2,0(sp)
800007ec: 00112623 sw ra,12(sp)
800007f0: 40245413 srai s0,s0,0x2
800007f4: 00000493 li s1,0
800007f8: 00078913 mv s2,a5
800007fc: 04849263 bne s1,s0,80000840 <__libc_init_array+0x78>
80000800: 879ff0ef jal ra,80000078 <_init>
80000804: 00000797 auipc a5,0x0
80000808: 06c78793 addi a5,a5,108 # 80000870 <__init_array_end>
8000080c: 00000417 auipc s0,0x0
80000810: 06440413 addi s0,s0,100 # 80000870 <__init_array_end>
80000814: 40f40433 sub s0,s0,a5
80000818: 40245413 srai s0,s0,0x2
8000081c: 00000493 li s1,0
80000820: 00078913 mv s2,a5
80000824: 02849a63 bne s1,s0,80000858 <__libc_init_array+0x90>
80000828: 00c12083 lw ra,12(sp)
8000082c: 00812403 lw s0,8(sp)
80000830: 00412483 lw s1,4(sp)
80000834: 00012903 lw s2,0(sp)
80000838: 01010113 addi sp,sp,16
8000083c: 00008067 ret
80000840: 00249793 slli a5,s1,0x2
80000844: 00f907b3 add a5,s2,a5
80000848: 0007a783 lw a5,0(a5)
8000084c: 00148493 addi s1,s1,1
80000850: 000780e7 jalr a5
80000854: fa9ff06f j 800007fc <__libc_init_array+0x34>
80000858: 00249793 slli a5,s1,0x2
8000085c: 00f907b3 add a5,s2,a5
80000860: 0007a783 lw a5,0(a5)
80000864: 00148493 addi s1,s1,1
80000868: 000780e7 jalr a5
8000086c: fb9ff06f j 80000824 <__libc_init_array+0x5c>
800007cc <halInit>:
800007cc: 00008067 ret
800007d0 <__libc_init_array>:
800007d0: ff010113 addi sp,sp,-16
800007d4: 00000797 auipc a5,0x0
800007d8: 0a478793 addi a5,a5,164 # 80000878 <__init_array_end>
800007dc: 00812423 sw s0,8(sp)
800007e0: 00000417 auipc s0,0x0
800007e4: 09840413 addi s0,s0,152 # 80000878 <__init_array_end>
800007e8: 40f40433 sub s0,s0,a5
800007ec: 00912223 sw s1,4(sp)
800007f0: 01212023 sw s2,0(sp)
800007f4: 00112623 sw ra,12(sp)
800007f8: 40245413 srai s0,s0,0x2
800007fc: 00000493 li s1,0
80000800: 00078913 mv s2,a5
80000804: 04849263 bne s1,s0,80000848 <__libc_init_array+0x78>
80000808: 871ff0ef jal ra,80000078 <_init>
8000080c: 00000797 auipc a5,0x0
80000810: 06c78793 addi a5,a5,108 # 80000878 <__init_array_end>
80000814: 00000417 auipc s0,0x0
80000818: 06440413 addi s0,s0,100 # 80000878 <__init_array_end>
8000081c: 40f40433 sub s0,s0,a5
80000820: 40245413 srai s0,s0,0x2
80000824: 00000493 li s1,0
80000828: 00078913 mv s2,a5
8000082c: 02849a63 bne s1,s0,80000860 <__libc_init_array+0x90>
80000830: 00c12083 lw ra,12(sp)
80000834: 00812403 lw s0,8(sp)
80000838: 00412483 lw s1,4(sp)
8000083c: 00012903 lw s2,0(sp)
80000840: 01010113 addi sp,sp,16
80000844: 00008067 ret
80000848: 00249793 slli a5,s1,0x2
8000084c: 00f907b3 add a5,s2,a5
80000850: 0007a783 lw a5,0(a5)
80000854: 00148493 addi s1,s1,1
80000858: 000780e7 jalr a5
8000085c: fa9ff06f j 80000804 <__libc_init_array+0x34>
80000860: 00249793 slli a5,s1,0x2
80000864: 00f907b3 add a5,s2,a5
80000868: 0007a783 lw a5,0(a5)
8000086c: 00148493 addi s1,s1,1
80000870: 000780e7 jalr a5
80000874: fb9ff06f j 8000082c <__libc_init_array+0x5c>

View file

@ -1,11 +1,11 @@
:0200000480007A
:100000001711000013010103170500001305057BFC
:10001000970500009385857A1716000013068681E0
:100000001711000013018111171500001305058752
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:10007000730020306F0000006780000073110134AE
:10008000232211002326310023284100232A510076
:10009000232C6100232E7100232081022322910250
@ -14,7 +14,7 @@
:1000C000232421052326310523284105232A510510
:1000D000232C6105232E71052320810723229107FC
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@ -23,113 +23,127 @@
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:1009080053757065727669736F72202A2A2A0A00F5
:040000058000000077
:00000001FF

View file

@ -209,11 +209,11 @@ void trap(){
case 0x1C: writeValue = max((unsigned int)src, (unsigned int)readValue); break;
default: redirectTrap(); return; break;
}
writeRegister(rd, readValue);
if(writeWord(addr, writeValue)){
emulationTrapToSupervisorTrap(mepc, mstatus);
return;
}
writeRegister(rd, readValue);
csr_write(mepc, mepc + 4);
csr_write(mtvec, trapEntry); //Restore mtvec
}break;