Merge pull request #69 from tomverbeure/micro_warnings

GenMicro with warnings

src/main/scala/vexriscv/demo/GenMicroNoCsr.scala

@@ -0,0 +1,61 @@
+package vexriscv.demo
+
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenMicroNoCsr extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      withMemoryStage = false,
+      withWriteBackStage = false,
+      plugins = List(
+        new IBusSimplePlugin(
+          resetVector = 0x80000000l,
+          cmdForkOnSecondStage = false,
+          cmdForkPersistence = false,
+          prediction = NONE,
+          catchAccessFault = false,
+          compressedGen = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false,
+          earlyInjection = false
+        ),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = false
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          zeroBoot = false,
+          writeRfInMemoryStage = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = false
+        ),
+        new LightShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = false,
+          bypassMemory            = false,
+          bypassWriteBack         = false,
+          bypassWriteBackBuffer   = false,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new BranchPlugin(
+          earlyBranch = true,
+          catchAddressMisaligned = false
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+  SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu())
+}

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -55,6 +55,7 @@ class BranchPlugin(earlyBranch : Boolean,
                    fenceiGenAsAJump : Boolean = false,
                    fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{
 
+
   def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN)
   lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
 
@@ -88,6 +89,8 @@ class BranchPlugin(earlyBranch : Boolean,
     import pipeline.config._
     import IntAluPlugin._
 
+    assert(earlyBranch || withMemoryStage, "earlyBranch must be true when memory stage is disabled!")
+
     val bActions = List[(Stageable[_ <: BaseType],Any)](
       SRC1_CTRL         -> Src1CtrlEnum.RS,
       SRC2_CTRL         -> Src2CtrlEnum.RS,
@@ -375,4 +378,4 @@ class BranchPlugin(earlyBranch : Boolean,
       }
     }
   }
-}
+}