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BmbGenerators refractoring (bus -> ctrl)

This commit is contained in:
Dolu1990 2020-07-16 13:04:25 +02:00
parent da73317912
commit fe5401f835
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -77,14 +77,14 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
val plicWishboneBridge = WishboneToBmbGenerator()
val plicWishbone = plicWishboneBridge.produceIo(plicWishboneBridge.logic.io.input)
plicWishboneBridge.config.load(WishboneConfig(20, 32))
interconnect.addConnection(plicWishboneBridge.bmb, plic.bus)
interconnect.addConnection(plicWishboneBridge.bmb, plic.ctrl)
val clint = BmbClintGenerator(0)
val clintWishboneBridge = WishboneToBmbGenerator()
val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.io.input)
clintWishboneBridge.config.load(WishboneConfig(14, 32))
interconnect.addConnection(clintWishboneBridge.bmb, clint.bus)
interconnect.addConnection(clintWishboneBridge.bmb, clint.ctrl)
val interrupts = add task (in Bits(32 bits))
for(i <- 1 to 31) yield plic.addInterrupt(interrupts.derivate(_.apply(i)), i)