XIP is physicaly working on murax
This commit is contained in:
Dolu1990
parent
b51ac03a5e
commit
ff1d1072a7
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@ -9,8 +9,8 @@ module toplevel(
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output io_B12,
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input io_B10,
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input io_P12,
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output io_P11,
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output io_P12,
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input io_P11,
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output io_R11,
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output io_R12,
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@ -46,9 +46,9 @@ module toplevel(
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wire [1:0] io_xpi_data_1_write;
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wire [0:0] io_xpi_ss;
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assign io_P11 = io_xpi_data_0_write[0];
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assign io_xpi_data_1_read[0] = io_P12;
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assign io_xpi_data_1_read[1] = io_P12;
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assign io_P12 = io_xpi_data_0_write[0];
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assign io_xpi_data_1_read[0] = io_P11;
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assign io_xpi_data_1_read[1] = io_P11;
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assign io_R11 = io_xpi_sclk_write[0];
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assign io_R12 = io_xpi_ss[0];
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@ -0,0 +1,6 @@
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*.bin
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*.elf
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*.map
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*.d
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*.asm
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*.o
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@ -0,0 +1,54 @@
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#define CTRL_BASE 0xF001F000
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#define XIP_BASE 0xE0040000
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#define CTRL_DATA 0x00
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#define CTRL_STATUS 0x04
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#define CTRL_MODE 0x08
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#define CTRL_RATE 0x20
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#define CTRL_SS_SETUP 0x24
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#define CTRL_SS_HOLD 0x28
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#define CTRL_SS_DISABLE 0x2C
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#define CTRL_XIP_CONFIG 0x40
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#define CTRL_XIP_MODE 0x44
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.global crtStart
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.global main
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#define CTRL x31
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crtStart:
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li x31, CTRL_BASE
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sw x0, CTRL_MODE(CTRL)
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li t0, 2
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sw t0, CTRL_RATE(CTRL)
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li t0, 4
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sw t0, CTRL_SS_SETUP(CTRL)
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sw t0, CTRL_SS_HOLD(CTRL)
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sw t0, CTRL_SS_DISABLE(CTRL)
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li a0, 0x880
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call spiWrite
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li a0, 0x181
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call spiWrite
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li a0, 0x183
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call spiWrite
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li a0, 0x800
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call spiWrite
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li t0, 0x00FF010B
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sw t0, CTRL_XIP_MODE(CTRL)
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li t0, 0x1
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sw t0, CTRL_XIP_CONFIG(CTRL)
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li t0, XIP_BASE
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jr t0
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spiWrite:
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sw a0,CTRL_DATA(CTRL)
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spiWrite_wait:
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lw t0,CTRL_STATUS(CTRL)
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srli t0,t0,0x10
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beqz t0,spiWrite_wait
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ret
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@ -0,0 +1,24 @@
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#define GPIO_BASE 0xF0000000
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#define GPIO_OUTPUT 4
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#define GPIO_OUTPUT_ENABLE 8
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.global crtStart
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crtStart:
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li x31, GPIO_BASE
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li t0, 0x000000FF
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sw t0, GPIO_OUTPUT_ENABLE(x31)
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li t0,0
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redo:
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sw t0, GPIO_OUTPUT(x31)
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li t1,10000
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addi t0,t0,1
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loop:
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addi t1,t1,-1
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bnez t1, loop
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j redo
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@ -0,0 +1,23 @@
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CFLAGS= -march=rv32i -mabi=ilp32 -g -O3 -MD
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LFLAGS= -nostdlib -mcmodel=medany -nostartfiles -ffreestanding -fPIC -fPIE
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all: crt.S demo.S
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riscv64-unknown-elf-gcc -c $(CFLAGS) -o crt.o crt.S
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riscv64-unknown-elf-gcc $(CFLAGS) -o crt.elf crt.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,crt.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d crt.elf > crt.asm
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riscv64-unknown-elf-objcopy -O binary crt.elf crt.bin
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riscv64-unknown-elf-gcc -c $(CFLAGS) -o demo.o demo.S
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riscv64-unknown-elf-gcc $(CFLAGS) -o demo.elf demo.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,demo.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d demo.elf > demo.asm
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riscv64-unknown-elf-objcopy -O binary demo.elf demo.bin
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clean:
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rm -f *.o
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rm -f *.bin
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rm -f *.elf
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rm -f *.asm
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rm -f *.map
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@ -0,0 +1,96 @@
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/*
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This is free and unencumbered software released into the public domain.
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Anyone is free to copy, modify, publish, use, compile, sell, or
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distribute this software, either in source code form or as a compiled
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binary, for any purpose, commercial or non-commercial, and by any
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means.
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*/
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(crtStart)
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MEMORY {
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mem : ORIGIN = 0x80000000, LENGTH = 0x00000400
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}
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_stack_size = DEFINED(_stack_size) ? _stack_size : 0;
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SECTIONS {
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.vector : {
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*crt.o(.text);
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} > mem
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.memory : {
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*(.text);
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end = .;
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} > mem
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} > mem
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.ctors :
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{
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. = ALIGN(4);
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_ctors_start = .;
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KEEP(*(.init_array*))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4);
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_ctors_end = .;
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} > mem
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.data :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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. = ALIGN(8);
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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. = ALIGN(8);
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} > mem
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.bss (NOLOAD) : {
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_bss_start = .;
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_bss_end = .;
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} > mem
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.noinit (NOLOAD) : {
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. = ALIGN(4);
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*(.noinit .noinit.*)
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. = ALIGN(4);
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} > mem
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._stack (NOLOAD):
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{
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. = ALIGN(16);
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PROVIDE (_stack_end = .);
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. = . + _stack_size;
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. = ALIGN(16);
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PROVIDE (_stack_start = .);
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} > mem
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}
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@ -44,18 +44,13 @@ case class MuraxConfig(coreFrequency : HertzNumber,
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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val genXpi = xipConfig != null
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def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters(
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SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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))
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}
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object MuraxConfig{
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def default = MuraxConfig(
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def default : MuraxConfig = default(false)
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def default(withXip : Boolean) = MuraxConfig(
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coreFrequency = 12 MHz,
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onChipRamSize = 8 kB,
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onChipRamHexFile = null,
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@ -63,10 +58,15 @@ object MuraxConfig{
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pipelineMainBus = false,
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pipelineApbBridge = true,
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gpioWidth = 32,
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xipConfig = null,
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xipConfig = ifGen(withXip) (SpiDdrMasterCtrl.MemoryMappingParameters(
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SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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)),
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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resetVector = if(withXip) 0xF001E000l else 0x80000000l,
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relaxedPcCalculation = true,
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prediction = NONE,
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catchAccessFault = false,
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@ -224,7 +224,9 @@ case class Murax(config : MuraxConfig) extends Component{
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val timerInterrupt = False
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val externalInterrupt = False
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for(plugin <- cpu.plugins) plugin match{
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case plugin : IBusSimplePlugin => mainBusArbiter.io.iBus <> plugin.iBus
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case plugin : IBusSimplePlugin =>
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mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd.halfPipe() //TODO !!
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mainBusArbiter.io.iBus.rsp <> plugin.iBus.rsp
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case plugin : DBusSimplePlugin => {
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if(!pipelineDBus)
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mainBusArbiter.io.dBus <> plugin.dBus
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@ -289,7 +291,7 @@ case class Murax(config : MuraxConfig) extends Component{
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apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
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val accessBus = new SimpleBus(SimpleBusConfig(24,32))
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mainBusMapping += accessBus -> (0x90000000l, 16 MB)
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mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
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ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr)
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ctrl.io.xip.cmd.ready <> accessBus.cmd.ready
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@ -297,6 +299,9 @@ case class Murax(config : MuraxConfig) extends Component{
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ctrl.io.xip.rsp.valid <> accessBus.rsp.valid
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ctrl.io.xip.rsp.payload <> accessBus.rsp.data
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val bootloader = Apb3Rom("src/main/c/murax/xipBootloader/crt.bin")
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apbMapping += bootloader.io.apb -> (0x1E000, 4 kB)
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})
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@ -327,7 +332,7 @@ object Murax{
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object MuraxWithXip{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.default.addXip()))
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SpinalVerilog(Murax(MuraxConfig.default(withXip = true)))
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}
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}
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@ -1,5 +1,7 @@
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package vexriscv.demo
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import java.nio.{ByteBuffer, ByteOrder}
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import spinal.core._
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import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
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import spinal.lib.bus.misc.SizeMapping
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@ -96,6 +98,27 @@ class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpl
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}
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case class Apb3Rom(onChipRamBinFile : String) extends Component{
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import java.nio.file.{Files, Paths}
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val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile))
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val wordCount = (byteArray.length+3)/4
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val buffer = ByteBuffer.wrap(Files.readAllBytes(Paths.get(onChipRamBinFile))).order(ByteOrder.LITTLE_ENDIAN);
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val wordArray = (0 until wordCount).map(i => {
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val v = buffer.getInt
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if(v < 0) BigInt(v.toLong & 0xFFFFFFFFl) else BigInt(v)
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})
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val io = new Bundle{
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val apb = slave(Apb3(log2Up(wordCount*4),32))
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}
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val rom = Mem(Bits(32 bits), wordCount) initBigInt(wordArray)
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// io.apb.PRDATA := rom.readSync(io.apb.PADDR >> 2)
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io.apb.PRDATA := rom.readAsync(RegNext(io.apb.PADDR >> 2))
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io.apb.PREADY := True
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}
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class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, simpleBusConfig : SimpleBusConfig) extends Component{
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assert(apb3Config.dataWidth == simpleBusConfig.dataWidth)
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@ -20,7 +20,7 @@ import scala.collection.mutable
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object MuraxSim {
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def main(args: Array[String]): Unit = {
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// def config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
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def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex").addXip()
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def config = MuraxConfig.default(withXip = true).copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
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val simSlowDown = true
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SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut =>
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val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
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