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VexRiscv
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wipe generator

This commit is contained in:
Charles Papon 2021-03-11 18:02:02 +01:00
parent adc37b269c
commit ff4e5e4666
5 changed files with 71 additions and 77 deletions
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35
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -17,7 +17,7 @@ object VexRiscvBmbGenerator{
val DEBUG_BMB = 4 val DEBUG_BMB = 4
} }
case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGenerator = null) extends Generator { case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGenerator = null) extends Area {
import VexRiscvBmbGenerator._ import VexRiscvBmbGenerator._
val config = Handle[VexRiscvConfig] val config = Handle[VexRiscvConfig]
@ -27,12 +27,12 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugAskReset = Handle[() => Unit] val debugAskReset = Handle[() => Unit]
val hardwareBreakpointCount = Handle(0) val hardwareBreakpointCount = Handle(0)
val iBus, dBus = product[Bmb] val iBus, dBus = Handle[Bmb]
val externalInterrupt = product[Bool] val externalInterrupt = Handle[Bool]
val externalSupervisorInterrupt = product[Bool] val externalSupervisorInterrupt = Handle[Bool]
val timerInterrupt = product[Bool] val timerInterrupt = Handle[Bool]
val softwareInterrupt = product[Bool] val softwareInterrupt = Handle[Bool]
def setTimerInterrupt(that: Handle[Bool]) = Dependable(that, timerInterrupt){timerInterrupt := that} def setTimerInterrupt(that: Handle[Bool]) = Dependable(that, timerInterrupt){timerInterrupt := that}
def setSoftwareInterrupt(that: Handle[Bool]) = Dependable(that, softwareInterrupt){softwareInterrupt := that} def setSoftwareInterrupt(that: Handle[Bool]) = Dependable(that, softwareInterrupt){softwareInterrupt := that}
@ -42,22 +42,21 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
withDebug.load(DEBUG_NONE) withDebug.load(DEBUG_NONE)
} }
def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG) withDebug.load(DEBUG_JTAG)
} }
def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG_CTRL) withDebug.load(DEBUG_JTAG_CTRL)
dependencies += jtagClockDomain
} }
def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
@ -66,7 +65,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugBmbAccessSource = Handle[BmbAccessCapabilities] val debugBmbAccessSource = Handle[BmbAccessCapabilities]
val debugBmbAccessRequirements = Handle[BmbAccessParameter] val debugBmbAccessRequirements = Handle[BmbAccessParameter]
def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd{ def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
@ -80,24 +79,16 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
) )
debugBmb.derivatedFrom(debugBmbAccessRequirements)(Bmb(_)) debugBmb.derivatedFrom(debugBmbAccessRequirements)(Bmb(_))
if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb) if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
dependencies += debugBmb
} }
dependencies ++= List(config) val jtag = Handle(withDebug.get == DEBUG_JTAG generate slave(Jtag()))
dependencies += Dependable(withDebug) {
if (withDebug.get != DEBUG_NONE) {
dependencies ++= List(debugClockDomain, debugAskReset)
}
}
val jtag = add task (withDebug.get == DEBUG_JTAG generate slave(Jtag()))
val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl()) val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl())
val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus()) val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus())
val debugBmb = Handle[Bmb] val debugBmb = Handle[Bmb]
val jtagClockDomain = Handle[ClockDomain] val jtagClockDomain = Handle[ClockDomain]
val logic = add task new Area { val logic = Handle(new Area {
withDebug.get != DEBUG_NONE generate new Area { withDebug.get != DEBUG_NONE generate new Area {
config.add(new DebugPlugin(debugClockDomain, hardwareBreakpointCount)) config.add(new DebugPlugin(debugClockDomain, hardwareBreakpointCount))
} }
@ -130,7 +121,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
} }
case _ => case _ =>
} }
} })
logic.soon(debugReset) logic.soon(debugReset)

13
src/main/scala/vexriscv/demo/Murax.scala
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@ -485,11 +485,10 @@ object Murax_arty{
} }
object MuraxAsicBlackBox{ object MuraxAsicBlackBox extends App{
def main(args: Array[String]) { println("Warning this soc do not has any rom to boot on.")
println("Warning this soc do not has any rom to boot on.") val config = SpinalConfig()
val config = SpinalConfig() config.addStandardMemBlackboxing(blackboxAll)
config.addStandardMemBlackboxing(blackboxAll) config.generateVerilog(Murax(MuraxConfig.default()))
config.generateVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB)))
}
} }

26
src/main/scala/vexriscv/demo/smp/Misc.scala
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@ -248,13 +248,13 @@ object BmbToLiteDramTester extends App{
} }
} }
case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{ case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Area{
val liteDramParameter = createDependency[LiteDramNativeParameter] val liteDramParameter = Handle[LiteDramNativeParameter]
val bmb = produce(logic.io.input) val bmb = Handle(logic.io.input)
val dram = produceIo(logic.io.output) val dram = Handle(logic.io.output.toIo)
val accessSource = Handle[BmbAccessCapabilities] val accessSource = Handle[BmbAccessCapabilities]
val accessRequirements = createDependency[BmbAccessParameter] val accessRequirements = Handle[BmbAccessParameter]
interconnect.addSlave( interconnect.addSlave(
accessSource = accessSource, accessSource = accessSource,
accessCapabilities = accessSource, accessCapabilities = accessSource,
@ -262,20 +262,20 @@ case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnec
bus = bmb, bus = bmb,
mapping = mapping mapping = mapping
) )
val logic = add task BmbToLiteDram( val logic = Handle(BmbToLiteDram(
bmbParameter = accessRequirements.toBmbParameter(), bmbParameter = accessRequirements.toBmbParameter(),
liteDramParameter = liteDramParameter, liteDramParameter = liteDramParameter,
wdataFifoSize = 32, wdataFifoSize = 32,
rdataFifoSize = 32 rdataFifoSize = 32
) ))
} }
case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{ case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Area{
val bmb = produce(logic.io.input) val bmb = Handle(logic.io.input)
val wishbone = produce(logic.io.output) val wishbone = Handle(logic.io.output)
val accessSource = Handle[BmbAccessCapabilities] val accessSource = Handle[BmbAccessCapabilities]
val accessRequirements = createDependency[BmbAccessParameter] val accessRequirements = Handle[BmbAccessParameter]
interconnect.addSlave( interconnect.addSlave(
accessSource = accessSource, accessSource = accessSource,
accessCapabilities = accessSource, accessCapabilities = accessSource,
@ -283,7 +283,7 @@ case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnec
bus = bmb, bus = bmb,
mapping = mapping mapping = mapping
) )
val logic = add task BmbToWishbone( val logic = Handle(BmbToWishbone(
p = accessRequirements.toBmbParameter() p = accessRequirements.toBmbParameter()
) ))
} }

10
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -27,7 +27,7 @@ import vexriscv.ip.fpu.FpuParameter
case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], withExclusiveAndInvalidation : Boolean, forcePeripheralWidth : Boolean = true, outOfOrderDecoder : Boolean = true) case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], withExclusiveAndInvalidation : Boolean, forcePeripheralWidth : Boolean = true, outOfOrderDecoder : Boolean = true)
class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator with PostInitCallback{ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with PostInitCallback{
val cpuCount = p.cpuConfigs.size val cpuCount = p.cpuConfigs.size
val debugCd = ClockDomainResetGenerator() val debugCd = ClockDomainResetGenerator()
@ -50,7 +50,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator
val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator() val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator()
debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false)) debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
val debugPort = debugBridge.produceIo(debugBridge.logic.jtagBridge.io.ctrl) val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo)
val dBusCoherent = BmbBridgeGenerator() val dBusCoherent = BmbBridgeGenerator()
val dBusNonCoherent = BmbBridgeGenerator() val dBusNonCoherent = BmbBridgeGenerator()
@ -87,7 +87,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator
class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends VexRiscvSmpClusterBase(p) { class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends VexRiscvSmpClusterBase(p) {
val peripheralBridge = BmbToWishboneGenerator(DefaultMapping) val peripheralBridge = BmbToWishboneGenerator(DefaultMapping)
val peripheral = peripheralBridge.produceIo(peripheralBridge.logic.io.output) val peripheral = Handle(peripheralBridge.logic.io.output.toIo)
if(p.forcePeripheralWidth) interconnect.slaves(peripheralBridge.bmb).forceAccessSourceDataWidth(32) if(p.forcePeripheralWidth) interconnect.slaves(peripheralBridge.bmb).forceAccessSourceDataWidth(32)
val plic = BmbPlicGenerator()(interconnect = null) val plic = BmbPlicGenerator()(interconnect = null)
@ -133,8 +133,8 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
} }
val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.bridge.io.input) val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.bridge.io.input)
val interrupts = add task (in Bits(32 bits)) val interrupts = in Bits(32 bits)
for(i <- 1 to 31) yield plic.addInterrupt(interrupts.derivate(_.apply(i)), i) for(i <- 1 to 31) yield plic.addInterrupt(interrupts(i), i)
for ((core, cpuId) <- cores.zipWithIndex) { for ((core, cpuId) <- cores.zipWithIndex) {
core.cpu.setTimerInterrupt(clint.timerInterrupt(cpuId)) core.cpu.setTimerInterrupt(clint.timerInterrupt(cpuId))

62
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -43,7 +43,7 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
// Coherent DMA interface // Coherent DMA interface
val dma = p.coherentDma generate new Area { val dma = p.coherentDma generate new Area {
val bridge = WishboneToBmbGenerator() val bridge = WishboneToBmbGenerator()
val wishbone = bridge.produceIo(bridge.logic.io.input) val wishbone = Handle(bridge.logic.io.input.toIo)
val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth
bridge.config.load(WishboneConfig( bridge.config.load(WishboneConfig(
addressWidth = 32 - log2Up(dataWidth / 8), addressWidth = 32 - log2Up(dataWidth / 8),
@ -128,9 +128,12 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
) )
def dutGen = { def dutGen = {
val toplevel = GeneratorComponent(new VexRiscvLitexSmpCluster( val toplevel = new Component {
p = parameter val body = new VexRiscvLitexSmpCluster(
)) p = parameter
)
body.setName("")
}
toplevel toplevel
} }
@ -200,29 +203,30 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
def dutGen = { def dutGen = {
import GeneratorComponent.toGenerator import GeneratorComponent.toGenerator
val top = new GeneratorComponent(new VexRiscvLitexSmpCluster( val top = new Component {
p = parameter val body = new VexRiscvLitexSmpCluster(
)) p = parameter
)
}
top.rework{ top.rework{
top.clintWishbone.setAsDirectionLess.allowDirectionLessIo top.body.clintWishbone.setAsDirectionLess.allowDirectionLessIo
top.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic() top.body.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
val hit = (top.peripheral.ADR <<2 >= 0xF0010000l && top.peripheral.ADR<<2 < 0xF0020000l) val hit = (top.body.peripheral.ADR <<2 >= 0xF0010000l && top.body.peripheral.ADR<<2 < 0xF0020000l)
top.clintWishbone.CYC := top.peripheral.CYC && hit top.body.clintWishbone.CYC := top.body.peripheral.CYC && hit
top.clintWishbone.STB := top.peripheral.STB top.body.clintWishbone.STB := top.body.peripheral.STB
top.clintWishbone.WE := top.peripheral.WE top.body.clintWishbone.WE := top.body.peripheral.WE
top.clintWishbone.ADR := top.peripheral.ADR.resized top.body.clintWishbone.ADR := top.body.peripheral.ADR.resized
top.clintWishbone.DAT_MOSI := top.peripheral.DAT_MOSI top.body.clintWishbone.DAT_MOSI := top.body.peripheral.DAT_MOSI
top.peripheral.DAT_MISO := top.clintWishbone.DAT_MISO top.body.peripheral.DAT_MISO := top.body.clintWishbone.DAT_MISO
top.peripheral.ACK := top.peripheral.CYC && (!hit || top.clintWishbone.ACK) top.body.peripheral.ACK := top.body.peripheral.CYC && (!hit || top.body.clintWishbone.ACK)
top.peripheral.ERR := False top.body.peripheral.ERR := False
// top.dMemBridge.unburstified.cmd.simPublic()
} }
top top
} }
simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut => simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
dut.debugCd.inputClockDomain.get.forkStimulus(10) dut.body.debugCd.inputClockDomain.get.forkStimulus(10)
val ram = SparseMemory() val ram = SparseMemory()
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin") ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
@ -231,16 +235,16 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio") ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
dut.iBridge.dram.simSlave(ram, dut.debugCd.inputClockDomain) dut.body.iBridge.dram.simSlave(ram, dut.body.debugCd.inputClockDomain)
dut.dBridge.dram.simSlave(ram, dut.debugCd.inputClockDomain/*, dut.dMemBridge.unburstified*/) dut.body.dBridge.dram.simSlave(ram, dut.body.debugCd.inputClockDomain/*, dut.body.dMemBridge.unburstified*/)
dut.interrupts.get #= 0 dut.body.interrupts #= 0
dut.debugCd.inputClockDomain.get.onFallingEdges{ dut.body.debugCd.inputClockDomain.get.onFallingEdges{
if(dut.peripheral.CYC.toBoolean){ if(dut.body.peripheral.CYC.toBoolean){
(dut.peripheral.ADR.toLong << 2) match { (dut.body.peripheral.ADR.toLong << 2) match {
case 0xF0000000l => print(dut.peripheral.DAT_MOSI.toLong.toChar) case 0xF0000000l => print(dut.body.peripheral.DAT_MOSI.toLong.toChar)
case 0xF0000004l => dut.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl) case 0xF0000004l => dut.body.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
case _ => case _ =>
} }
} }