DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
This commit is contained in:
Dolu1990
parent
7ffbfab312
commit
ff760a0bf0
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@ -41,7 +41,8 @@ object TestsWorkspace {
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// ),
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = true,
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compressedGen = false,
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prediction = DYNAMIC_TARGET,
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config = InstructionCacheConfig(
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cacheSize = 1024*16,
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bytePerLine = 32,
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@ -53,6 +53,8 @@ object BrieyConfig{
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// catchAccessFault = true
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// ),
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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prediction = STATIC,
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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@ -64,7 +66,8 @@ object BrieyConfig{
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoCycleRam = true
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twoCycleRam = true,
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twoCycleCache = true
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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@ -123,7 +126,7 @@ object BrieyConfig{
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = STATIC
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prediction = NONE
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),
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new CsrPlugin(
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config = CsrPluginConfig(
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@ -32,13 +32,13 @@ case class FetchPredictionCmd() extends Bundle{
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val hadBranch = Bool
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val targetPc = UInt(32 bits)
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}
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case class FetchPredictionRsp(stage : Stage) extends Bundle{
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case class FetchPredictionRsp() extends Bundle{
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val wasRight = Bool
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val targetPc = UInt(32 bits)
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val finalPc = UInt(32 bits)
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}
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case class FetchPredictionBus(stage : Stage) extends Bundle {
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val cmd = FetchPredictionCmd()
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val rsp = FetchPredictionRsp(stage)
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val rsp = FetchPredictionRsp()
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}
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@ -68,9 +68,14 @@ class BranchPlugin(earlyBranch : Boolean,
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var decodePrediction : DecodePredictionBus = null
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var fetchPrediction : FetchPredictionBus = null
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override def askFetchPrediction() = ???
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override def askFetchPrediction() = {
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fetchPrediction = FetchPredictionBus(branchStage)
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fetchPrediction
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}
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override def askDecodePrediction() = {
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decodePrediction = DecodePredictionBus(branchStage)
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decodePrediction
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@ -131,9 +136,10 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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}
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override def build(pipeline: VexRiscv): Unit = (decodePrediction) match {
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case null => buildWithoutPrediction(pipeline)
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case _ => buildWithPrediction(pipeline)
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override def build(pipeline: VexRiscv): Unit = (fetchPrediction,decodePrediction) match {
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case (null, null) => buildWithoutPrediction(pipeline)
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case (_ , null) => buildFetchPrediction(pipeline)
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case (null, _) => buildDecodePrediction(pipeline)
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// case `DYNAMIC` => buildWithPrediction(pipeline)
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// case `DYNAMIC_TARGET` => buildDynamicTargetPrediction(pipeline)
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}
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@ -192,7 +198,7 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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def buildWithPrediction(pipeline: VexRiscv): Unit = {
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def buildDecodePrediction(pipeline: VexRiscv): Unit = {
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// case class BranchPredictorLine() extends Bundle{
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// val history = SInt(historyWidth bits)
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// }
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@ -298,9 +304,9 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) jumpInterface.payload(0 downto 0) =/= 0 else jumpInterface.payload(1 downto 0) =/= 0)
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) input(BRANCH_CALC)(0 downto 0) =/= 0 else input(BRANCH_CALC)(1 downto 0) =/= 0)
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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branchExceptionPort.badAddr := input(BRANCH_CALC)
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}
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}
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@ -321,139 +327,64 @@ class BranchPlugin(earlyBranch : Boolean,
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// def buildDynamicTargetPrediction(pipeline: VexRiscv): Unit = {
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// import pipeline._
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// import pipeline.config._
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//
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// case class BranchPredictorLine() extends Bundle{
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// val source = Bits(31 - historyRamSizeLog2 bits)
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// val confidence = UInt(2 bits)
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// val target = UInt(32 bits)
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// }
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//
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// object PREDICTION_WRITE_HAZARD extends Stageable(Bool)
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// object PREDICTION extends Stageable(BranchPredictorLine())
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// object PREDICTION_HIT extends Stageable(Bool)
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//
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// val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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// val historyWrite = history.writePort
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//
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//
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// fetch plug new Area{
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// import fetch._
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// val line = history.readSync((prefetch.output(PC) >> 2).resized, prefetch.arbitration.isFiring)
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//// val line = history.readAsync((fetch.output(PC) >> 2).resized)
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// val hit = line.source === (input(PC).asBits >> 1 + historyRamSizeLog2)
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//
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// //Avoid write to read hazard
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// val historyWriteLast = RegNext(historyWrite)
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// val hazard = historyWriteLast.valid && historyWriteLast.address === (output(PC) >> 2).resized
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// insert(PREDICTION_WRITE_HAZARD) := hazard
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//
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// predictionJumpInterface.valid := line.confidence.msb && hit && arbitration.isFiring && !hazard
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// predictionJumpInterface.payload := line.target
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//
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// insert(PREDICTION) := line
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// insert(PREDICTION_HIT) := hit
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// }
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//
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//
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//
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// //Do branch calculations (conditions + target PC)
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// execute plug new Area {
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// import execute._
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//
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// val less = input(SRC_LESS)
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// val eq = input(SRC1) === input(SRC2)
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//
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// insert(BRANCH_DO) := input(BRANCH_CTRL).mux(
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// BranchCtrlEnum.INC -> False,
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// BranchCtrlEnum.JAL -> True,
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// BranchCtrlEnum.JALR -> True,
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// BranchCtrlEnum.B -> input(INSTRUCTION)(14 downto 12).mux(
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// B"000" -> eq ,
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// B"001" -> !eq ,
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// M"1-1" -> !less,
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// default -> less
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// )
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// )
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//
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// val imm = IMM(input(INSTRUCTION))
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// val branch_src1 = (input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? input(RS1).asUInt | input(PC)
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// val branch_src2 = input(BRANCH_CTRL).mux(
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// BranchCtrlEnum.JAL -> imm.j_sext,
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// BranchCtrlEnum.JALR -> imm.i_sext,
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// default -> imm.b_sext
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// ).asUInt
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//
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// val branchAdder = branch_src1 + branch_src2
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// insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0))
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// }
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//
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// //Apply branchs (JAL,JALR, Bxx)
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// val branchStage = if(earlyBranch) execute else memory
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// branchStage plug new Area {
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// import branchStage._
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//
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// val predictionMissmatch = input(PREDICTION).confidence.msb =/= input(BRANCH_DO) || (input(BRANCH_DO) && input(PREDICTION).target =/= input(BRANCH_CALC))
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//
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// historyWrite.valid := False
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// historyWrite.address := (branchStage.output(PC) >> 2).resized
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// historyWrite.data.source := input(PC).asBits >> 1 + historyRamSizeLog2
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// historyWrite.data.target := input(BRANCH_CALC)
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//
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// jumpInterface.valid := False
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// jumpInterface.payload := input(BRANCH_CALC)
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//
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//
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// when(!input(BRANCH_DO)){
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// historyWrite.valid := arbitration.isFiring && input(PREDICTION_HIT)
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// historyWrite.data.confidence := input(PREDICTION).confidence - (input(PREDICTION).confidence =/= 0).asUInt
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// historyWrite.data.target := input(BRANCH_CALC)
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//
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//
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// jumpInterface.valid := input(PREDICTION_HIT) && input(PREDICTION).confidence.msb && !input(PREDICTION_WRITE_HAZARD) && arbitration.isFiring
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// jumpInterface.payload := input(PC) + 4
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// } otherwise{
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// when(!input(PREDICTION_HIT) || input(PREDICTION_WRITE_HAZARD)){
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// jumpInterface.valid := arbitration.isFiring
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// historyWrite.valid := arbitration.isFiring
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// historyWrite.data.confidence := "10"
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// } otherwise {
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// historyWrite.valid := arbitration.isFiring
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// historyWrite.data.confidence := input(PREDICTION).confidence + (input(PREDICTION).confidence =/= 3).asUInt
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// when(!input(PREDICTION).confidence.msb || input(PREDICTION).target =/= input(BRANCH_CALC)){
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// jumpInterface.valid := arbitration.isFiring
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// }
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// }
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// }
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//
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// //Prevent rewriting an history which already had hazard
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// historyWrite.valid clearWhen(input(PREDICTION_WRITE_HAZARD))
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//
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//
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//
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// when(jumpInterface.valid) {
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// stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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// }
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//
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// if(catchAddressMisaligned) {
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// branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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// branchExceptionPort.code := 0
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// branchExceptionPort.badAddr := jumpInterface.payload
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// }
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// }
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//
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// //Init History
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// val historyInit = pipeline plug new Area{
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// val counter = Reg(UInt(historyRamSizeLog2 + 1 bits)) init(0)
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// when(!counter.msb){
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// prefetch.arbitration.haltByOther := True
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// historyWrite.valid := True
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// historyWrite.address := counter.resized
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// historyWrite.data.confidence := 0
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// counter := counter + 1
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// }
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// }
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// }
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def buildFetchPrediction(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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//Do branch calculations (conditions + target PC)
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execute plug new Area {
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import execute._
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val less = input(SRC_LESS)
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val eq = input(SRC1) === input(SRC2)
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insert(BRANCH_DO) := input(BRANCH_CTRL).mux(
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BranchCtrlEnum.INC -> False,
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BranchCtrlEnum.JAL -> True,
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BranchCtrlEnum.JALR -> True,
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BranchCtrlEnum.B -> input(INSTRUCTION)(14 downto 12).mux(
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B"000" -> eq ,
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B"001" -> !eq ,
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M"1-1" -> !less,
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default -> less
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)
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)
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val imm = IMM(input(INSTRUCTION))
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val branch_src1 = (input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? input(RS1).asUInt | input(PC)
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val branch_src2 = input(BRANCH_CTRL).mux(
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BranchCtrlEnum.JAL -> imm.j_sext,
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BranchCtrlEnum.JALR -> imm.i_sext,
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default -> imm.b_sext
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).asUInt
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val branchAdder = branch_src1 + branch_src2
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insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0))
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}
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//Apply branchs (JAL,JALR, Bxx)
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val branchStage = if(earlyBranch) execute else memory
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branchStage plug new Area {
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import branchStage._
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val predictionMissmatch = fetchPrediction.cmd.hadBranch =/= input(BRANCH_DO) || (input(BRANCH_DO) && fetchPrediction.cmd.targetPc =/= input(BRANCH_CALC))
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fetchPrediction.rsp.wasRight := ! predictionMissmatch
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fetchPrediction.rsp.finalPc := input(BRANCH_CALC)
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jumpInterface.valid := arbitration.isFiring && predictionMissmatch //Probably just isValid instead of isFiring is better
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jumpInterface.payload := (input(BRANCH_DO) ? input(BRANCH_CALC) | input(PC) + (if(pipeline(RVC_GEN)) ((input(IS_RVC)) ? U(2) | U(4)) else 4))
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when(jumpInterface.valid) {
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) input(BRANCH_CALC)(0 downto 0) =/= 0 else input(BRANCH_CALC)(1 downto 0) =/= 0)
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := input(BRANCH_CALC)
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}
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}
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}
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}
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@ -22,6 +22,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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var decodePrediction : DecodePredictionBus = null
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var fetchPrediction : FetchPredictionBus = null
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assert(cmdToRspStageCount >= 1)
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assert(!(cmdToRspStageCount == 1 && !injectorStage))
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assert(!(compressedGen && !decodePcGen))
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@ -68,6 +69,9 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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case DYNAMIC_TARGET => {
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fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
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}
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}
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}
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@ -98,6 +102,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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class PcFetch extends Area{
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val preOutput = Stream(UInt(32 bits))
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val output = preOutput.haltWhen(fetcherHalt)
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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}
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val fetchPc = if(relaxedPcCalculation) new PcFetch {
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@ -117,6 +122,11 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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//application of the selected jump request
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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pcReg := predictionPcLoad.payload
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}
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}
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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@ -131,6 +141,13 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val pc = pcReg + (inc ## B"00").asUInt
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val samplePcNext = False
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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inc := False
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samplePcNext := True
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pc := predictionPcLoad.payload
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}
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}
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when(jump.pcLoad.valid) {
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inc := False
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samplePcNext := True
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@ -252,26 +269,26 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val inputBeforeHalt = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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if (injectorReadyCutGen) {
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iBusRsp.readyForError.clearWhen(inputBeforeHalt.valid)
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incomingInstruction setWhen (inputBeforeHalt.valid)
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iBusRsp.readyForError.clearWhen(inputBeforeStage.valid)
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incomingInstruction setWhen (inputBeforeStage.valid)
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}
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val decodeInput = (if (injectorStage) {
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val decodeInput = inputBeforeHalt.m2sPipeWithFlush(killLastStage, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeHalt.rsp.inst)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(killLastStage, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid)
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incomingInstruction setWhen (decodeInput.valid)
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decodeInput
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} else {
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inputBeforeHalt
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inputBeforeStage
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})
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if (decodePcGen) {
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decodeNextPcValid := True
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decodeNextPc := decodePc.pcReg
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} else {
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val lastStageStream = if (injectorStage) inputBeforeHalt
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val lastStageStream = if (injectorStage) inputBeforeStage
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else if (cmdToRspStageCount > 1) iBusRsp.inputPipeline(cmdToRspStageCount - 2)
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else throw new Exception("Fetch should at least have two stages")
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@ -354,7 +371,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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}
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prediction match {
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val predictor = prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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def historyWidth = 2
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@ -393,6 +410,67 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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// predictionExceptionPort.badAddr := predictionJumpInterface.payload
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}
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}
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case DYNAMIC_TARGET => new Area{
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val historyRamSizeLog2 : Int = 10
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case class BranchPredictorLine() extends Bundle{
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val source = Bits(31 - historyRamSizeLog2 bits)
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val branchWish = UInt(2 bits)
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val target = UInt(32 bits)
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}
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = history.writePort
|
||||
|
||||
val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready)
|
||||
val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 1 + historyRamSizeLog2)
|
||||
|
||||
//Avoid write to read hazard
|
||||
val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.inputPipeline(0).ready)
|
||||
val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.inputPipeline(0).payload >> 2).resized
|
||||
fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && iBusRsp.inputPipeline(0).fire && !flush && !hazard
|
||||
fetchPc.predictionPcLoad.payload := line.target
|
||||
|
||||
case class PredictionResult() extends Bundle{
|
||||
val hazard = Bool
|
||||
val hit = Bool
|
||||
val line = BranchPredictorLine()
|
||||
}
|
||||
|
||||
val fetchContext = PredictionResult()
|
||||
fetchContext.hazard := hazard
|
||||
fetchContext.hit := hit
|
||||
fetchContext.line := line //RegNextWhen(e._1, e._2.)
|
||||
val iBusRspContext = iBusRsp.inputPipeline.tail.foldLeft(fetchContext)((data,stream) => RegNextWhen(data, stream.ready))
|
||||
val injectorContext = Delay(iBusRspContext,cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
|
||||
|
||||
object PREDICTION_CONTEXT extends Stageable(PredictionResult())
|
||||
pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
|
||||
val branchStage = fetchPrediction.stage
|
||||
val branchContext = branchStage.input(PREDICTION_CONTEXT)
|
||||
fetchPrediction.cmd.hadBranch := branchContext.hit && !branchContext.hazard && branchContext.line.branchWish.msb
|
||||
fetchPrediction.cmd.targetPc := branchContext.line.target
|
||||
|
||||
|
||||
historyWrite.valid := False
|
||||
historyWrite.address := (branchStage.input(PC) >> 2).resized
|
||||
historyWrite.data.source := branchStage.input(PC).asBits >> 1 + historyRamSizeLog2
|
||||
historyWrite.data.target := fetchPrediction.rsp.finalPc
|
||||
|
||||
when(fetchPrediction.rsp.wasRight) {
|
||||
historyWrite.valid := branchContext.hit
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish + (branchContext.line.branchWish === 2).asUInt - (branchContext.line.branchWish === 1).asUInt
|
||||
} otherwise {
|
||||
when(branchContext.hit) {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish - (branchContext.line.branchWish.msb).asUInt + (!branchContext.line.branchWish.msb).asUInt
|
||||
} otherwise {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := "10"
|
||||
}
|
||||
}
|
||||
|
||||
historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue