47 lines
1.6 KiB
Tcl
47 lines
1.6 KiB
Tcl
#Create output directory and clear contents
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source [file join [file dirname [file normalize [info script]]] vivado_params.tcl]
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file mkdir $outputdir
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set files [glob -nocomplain "$outputdir/*"]
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if {[llength $files] != 0} {
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puts "deleting contents of $outputdir"
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file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
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} else {
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puts "$outputdir is empty"
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}
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#Create project
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create_project -part $part $projectName $outputdir
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#add source files to Vivado project
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#add_files -fileset sim_1 ./path/to/testbench.vhd
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#add_files [glob ./path/to/sources/*.vhd]
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#add_files -fileset constrs_1 ./path/to/constraint/constraint.xdc
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#add_files [glob ./path/to/library/sources/*.vhd]
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#set_property -library userDefined [glob ./path/to/library/sources/*.vhd]
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add_files [glob $base/*.v]
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add_files [glob $topv]
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add_files -fileset constrs_1 $base/arty_a7.xdc
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#set top level module and update compile order
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set_property top toplevel [current_fileset]
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update_compile_order -fileset sources_1
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#update_compile_order -fileset sim_1
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#launch synthesis
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launch_runs synth_1
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wait_on_run synth_1
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#Run implementation and generate bitstream
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set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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puts "Implementation done!"
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#reports generated by default
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#open_run impl_1
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#report_timing_summary -check_timing_verbose -report_unconstrained -file report_timing_summary.rpt
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#report_utilization -hierarchical -file report_utilization.rpt
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#TODO: add checks about timing, DRC, CDC such that the script give clear indication if design is OK or not
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