40 lines
929 B
Verilog
40 lines
929 B
Verilog
`timescale 1ns / 1ps
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module toplevel(
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input CLK,
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input BUT1,
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input BUT2,
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output LED1,
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output LED2
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);
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assign LED1 = io_gpioA_write[0];
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assign LED2 = io_gpioA_write[7];
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wire [31:0] io_gpioA_read;
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wire [31:0] io_gpioA_write;
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wire [31:0] io_gpioA_writeEnable;
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wire io_mainClk;
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// Use PLL to downclock external clock.
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toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK),
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.PLLOUTCORE(io_mainClk),
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.PLLOUTGLOBAL(),
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.RESET(1'b1));
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Murax murax (
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.io_asyncReset(1'b0),
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.io_mainClk (io_mainClk),
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.io_jtag_tck(1'b0),
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.io_jtag_tdi(1'b0),
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.io_jtag_tdo(),
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.io_jtag_tms(1'b0),
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.io_gpioA_read (io_gpioA_read),
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.io_gpioA_write (io_gpioA_write),
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.io_gpioA_writeEnable(io_gpioA_writeEnable),
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.io_uart_txd(),
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.io_uart_rxd(0'b0)
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);
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endmodule
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