VexRiscv/scripts/Murax/arty_a7/vivado_params.tcl
2020-01-17 00:33:02 +01:00

5 lines
131 B
Tcl

set outputdir ./vivado_project
set part "xc7a35ticsg324-1L"
set base ".."
set projectName "fpga"
set topv "$base/../../../Murax.v"