mirror of
https://github.com/SpinalHDL/VexRiscv.git
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5b8febb977
This reverts commit c01c256757.
Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
31 lines
1 KiB
Tcl
31 lines
1 KiB
Tcl
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# Input file
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set source_bit_file "./latest.bit"
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# Output file
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set output_mcs_file "./latest.mcs"
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# Delete target file
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file delete -force $output_mcs_file
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# Determine if the user has built the project and has the target source file
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# If not, then use the reference bit file shipped with the project
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if { ![file exists $source_bit_file] } {
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puts "\n********************************************"
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puts "INFO - File $source_bit_file doesn't exist as project has not been built\n"
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puts "********************************************/n"
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error
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}
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# Create MCS file for base board QSPI flash memory
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write_cfgmem -force -format MCS -size 16 -interface SPIx4 -loadbit " up 0 $source_bit_file" $output_mcs_file
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# Check MCS was correctly made
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if { ![file exists $output_mcs_file] } {
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puts "ERROR - $output_bit_file not made"
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return -1
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} else {
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puts "\n********************************************"
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puts " $output_mcs_file correctly generated"
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puts "********************************************\n"
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}
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