mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
5b8febb977
This reverts commit c01c256757.
Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
5 lines
131 B
Tcl
5 lines
131 B
Tcl
set outputdir ./vivado_project
|
|
set part "xc7a35ticsg324-1L"
|
|
set base ".."
|
|
set projectName "fpga"
|
|
set topv "$base/../../../Murax.v"
|