41 lines
913 B
Verilog
41 lines
913 B
Verilog
`timescale 1ns / 1ps
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module toplevel(
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input io_J3,
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input io_H16,
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input io_G15,
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output io_G16,
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input io_F15,
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output [7:0] io_led
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);
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wire [31:0] io_gpioA_read;
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wire [31:0] io_gpioA_write;
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wire [31:0] io_gpioA_writeEnable;
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wire io_mainClk;
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wire io_jtag_tck;
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SB_GB mainClkBuffer (
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.USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3),
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.GLOBAL_BUFFER_OUTPUT ( io_mainClk)
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);
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SB_GB jtagClkBuffer (
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.USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16),
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.GLOBAL_BUFFER_OUTPUT ( io_jtag_tck)
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);
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assign io_led = io_gpioA_write[7 : 0];
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Murax murax (
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.io_asyncReset(0),
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.io_mainClk (io_mainClk ),
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.io_jtag_tck(io_jtag_tck),
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.io_jtag_tdi(io_G15),
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.io_jtag_tdo(io_G16),
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.io_jtag_tms(io_F15),
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.io_gpioA_read (io_gpioA_read),
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.io_gpioA_write (io_gpioA_write),
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.io_gpioA_writeEnable(io_gpioA_writeEnable)
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);
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endmodule |