mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
50 lines
No EOL
448 B
Text
50 lines
No EOL
448 B
Text
*.class
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*.log
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*.bak
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# sbt specific
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.cache/
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.history/
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.lib/
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dist/*
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target
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lib_managed/
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src_managed/
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project/boot/
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project/plugins/project/
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# Scala-IDE specific
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.scala_dependencies
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.worksheet
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.idea
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out
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# Eclipse
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bin/
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.classpath
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.project
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.cproject
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.settings
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.cache-main
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#User
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/*.vhd
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/*.v
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*.cf
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*.json
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*.vcd
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!tester/src/test/resources/*.vhd
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obj_dir
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*.logTrace
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*.yaml
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*.memTrace
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*.regTrace
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*.tcl
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*.o
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*.bin
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simWorkspace/
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tmp/
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/archive.tar.gz
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*.out32 |