29 lines
562 B
Systemverilog
29 lines
562 B
Systemverilog
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`timescale 1ns / 1ps `default_nettype none
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module timer #(
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parameter MOD_VALUE = 1,
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parameter BIT_WIDTH = 1
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) (
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input wire logic clk,
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reset,
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increment,
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output logic rolling_over,
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output logic [BIT_WIDTH-1:0] count = 0
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);
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always_ff @(posedge clk) begin
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if (reset) count <= 0;
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else if (increment) begin
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if (rolling_over) count <= 0;
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else count <= count + 1'b1;
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end
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end
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always_comb begin
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if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1;
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else rolling_over = 1'b0;
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end
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endmodule
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