15 lines
252 B
Verilog
15 lines
252 B
Verilog
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module PWM (
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input wire clk,
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input wire [13:0] width,
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output reg pulse
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);
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reg [13:0] counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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if (counter < width) pulse <= 1'b1;
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else pulse <= 1'b0;
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end
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endmodule
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