26 lines
466 B
Verilog
26 lines
466 B
Verilog
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module top (
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input clk,
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input rx,
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output tx,
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input [15:0] sw,
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output [15:0] led
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);
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localparam BITS = 4;
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localparam LOG2DELAY = 22;
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wire bufg;
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BUFG bufgctrl(.I(clk), .O(bufg));
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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always @(posedge bufg) begin
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counter <= counter + 1;
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end
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assign led[3:0] = counter >> LOG2DELAY;
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assign led[14:4] = sw[14:4];
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assign tx = rx;
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assign led[15] = ^sw;
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endmodule
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