72 lines
1.4 KiB
Systemverilog
72 lines
1.4 KiB
Systemverilog
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`timescale 1ns / 1ps `default_nettype none
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module top (
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input wire logic clk,
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btnu,
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btnc,
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output logic [3:0] anode,
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output logic [7:0] segment
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);
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logic sync;
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logic syncToDebounce;
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logic debounceToOneShot;
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logic f1, f2;
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logic f3, f4;
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logic oneShotToCounter;
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logic [7:0] counterToSevenSegment;
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logic [7:0] counterToSevenSegment2;
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logic oneShotToCounter2;
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logic s0, s1;
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debounce d0 (
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.clk(clk),
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.reset(btnu),
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.noisy(syncToDebounce),
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.debounced(debounceToOneShot)
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);
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assign oneShotToCounter = f1 && ~f2;
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assign oneShotToCounter2 = f3 && ~f4;
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timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T0 (
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.clk(clk),
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.reset(btnu),
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.increment(oneShotToCounter),
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.rolling_over(s0),
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.count(counterToSevenSegment)
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);
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timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T1 (
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.clk(clk),
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.reset(btnu),
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.increment(oneShotToCounter2),
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.rolling_over(s1),
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.count(counterToSevenSegment2)
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);
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display_control DC0 (
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.clk(clk),
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.reset(btnu),
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.dataIn({counterToSevenSegment2, counterToSevenSegment}),
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.digitDisplay(4'b1111),
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.digitPoint(4'b0000),
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.anode(anode),
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.segment(segment)
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);
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always_ff @(posedge clk) begin
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sync <= btnc;
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syncToDebounce <= sync;
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f1 <= debounceToOneShot;
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f2 <= f1;
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f3 <= syncToDebounce;
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f4 <= f3;
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end
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endmodule
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