33 lines
618 B
Verilog
33 lines
618 B
Verilog
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module top (
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input wire clk,
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input wire [3:0] sw,
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input wire [3:0] btn,
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output wire pulse_red,
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pulse_blue,
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pulse_green
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);
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wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG;
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assign pulse_wideR = {1'b0, sw[3:1], 10'd0};
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assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0};
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assign pulse_wideB = {btn[1:0], 11'd0};
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PWM R0 (
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.clk (clk),
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.pulse(pulse_red),
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.width(pulse_wideR)
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);
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PWM B0 (
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.clk (clk),
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.pulse(pulse_green),
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.width(pulse_wideB)
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);
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PWM G0 (
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.clk (clk),
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.pulse(pulse_blue),
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.width(pulse_wideG)
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);
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endmodule
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