30 lines
642 B
Systemverilog
30 lines
642 B
Systemverilog
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`default_nettype none
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module mod_counter #(parameter MOD_VALUE=10) (
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input wire logic clk, reset, increment,
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output logic rolling_over,
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output logic[3:0] count = 0
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);
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always_ff @(posedge clk)
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begin
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if(reset)
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count <= 4'b0000;
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else if(increment)
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begin
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if(rolling_over)
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count <= 4'b0000;
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else
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count <= count + 4'b0001;
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end
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end
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always_comb
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begin
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if(increment && (count==MOD_VALUE-1))
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rolling_over = 1'b1;
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else
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rolling_over = 1'b0;
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end
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endmodule
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