Merge pull request #145 from cjearls/addingNexys4DDRtoPicoSoCSigned
adding support for the Nexys4DDR to PicoSoC example
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commit
043e59355f
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@ -23,6 +23,12 @@ else ifeq ($(TARGET),arty_100)
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PCF:=${current_dir}/arty.pcf
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DEVICE := xc7a100t_test
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BOARD_BUILDDIR := ${BUILDDIR}/arty_100
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else ifeq ($(TARGET),nexys4ddr)
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VERILOG += ${current_dir}/nexys4ddr.v
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PARTNAME := xc7a100tcsg324-1
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PCF:=${current_dir}/nexys4ddr.pcf
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DEVICE := xc7a100t_test
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BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
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else
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VERILOG += ${current_dir}/basys3.v
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PARTNAME := xc7a35tcpg236-1
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@ -16,6 +16,12 @@ picosoc example, run the following commands:
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TARGET="arty_100" make -C picosoc_demo
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.. code-block:: bash
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:name: example-picosoc-nexys4ddr-group
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TARGET="nexys4ddr" make -C picosoc_demo
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.. code-block:: bash
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:name: example-picosoc-basys3-group
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@ -0,0 +1,42 @@
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# 100 MHz CLK
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set_io clk E3
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# UART rx and tx are assigned to pins 1 and 2 of the PMOD Jumper C
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set_io rx C4
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set_io tx D4
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# LEDs
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set_io led[0] H17
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set_io led[1] K15
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set_io led[2] J13
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set_io led[3] N14
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set_io led[4] R18
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set_io led[5] V17
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set_io led[6] U17
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set_io led[7] U16
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set_io led[8] V16
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set_io led[9] T15
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set_io led[10] U14
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set_io led[11] T16
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set_io led[12] V15
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set_io led[13] V14
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set_io led[14] V12
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set_io led[15] V11
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# SWs
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set_io sw[0] J15
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set_io sw[1] L16
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set_io sw[2] M13
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set_io sw[3] R15
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set_io sw[4] R17
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set_io sw[5] T18
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set_io sw[6] U18
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set_io sw[7] R13
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set_io sw[8] T8
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set_io sw[9] U8
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set_io sw[10] R16
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set_io sw[11] T13
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set_io sw[12] H6
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set_io sw[13] U12
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set_io sw[14] U11
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set_io sw[15] V10
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@ -0,0 +1,86 @@
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/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module top (
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input clk,
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output tx,
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input rx,
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input [15:0] sw,
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output [15:0] led,
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);
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wire clk_bufg;
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BUFG bufg (.I(clk), .O(clk_bufg));
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk_bufg) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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wire iomem_valid;
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reg iomem_ready;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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reg [31:0] iomem_rdata;
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reg [31:0] gpio;
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assign led = gpio[15:0];
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always @(posedge clk_bufg) begin
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if (!resetn) begin
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gpio <= 0;
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end else begin
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iomem_ready <= 0;
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if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
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iomem_ready <= 1;
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iomem_rdata <= {sw, gpio[15:0]};
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if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
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if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
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if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
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if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
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end
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end
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end
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picosoc_noflash soc (
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.clk (clk_bufg),
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.resetn (resetn ),
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.ser_tx (tx),
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.ser_rx (rx),
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.irq_5 (1'b0 ),
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.irq_6 (1'b0 ),
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.irq_7 (1'b0 ),
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.iomem_valid (iomem_valid ),
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.iomem_ready (iomem_ready ),
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.iomem_wstrb (iomem_wstrb ),
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.iomem_addr (iomem_addr ),
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.iomem_wdata (iomem_wdata ),
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.iomem_rdata (iomem_rdata )
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);
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endmodule
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