Merge pull request #351 from antmicro/umarcor/eos-s3/dump

eos-s3/btn_counter/Makefile: dump jlink,openocd,header,binary

common/requirements.txt

@@ -15,4 +15,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 python-constraint
-https://github.com/chipsalliance/f4pga/archive/c342fc6ff1684f3dc6072713730ac9fc574ab2f3.zip#subdirectory=f4pga
+https://github.com/chipsalliance/f4pga/archive/cad8afe0842cd73f5b73949fa12eab1fda326055.zip#subdirectory=f4pga

docs/building-examples.rst

@@ -20,14 +20,14 @@ Select your FPGA family:
       .. code-block:: bash
          :name: fpga-fam-xc7
 
-         FPGA_FAM="xc7"
+         export FPGA_FAM="xc7"
 
    .. group-tab:: EOS S3
 
       .. code-block:: bash
          :name: fpga-fam-eos-s3
 
-         FPGA_FAM="eos-s3"
+         export FPGA_FAM="eos-s3"
 
 Next, prepare the environment:
 

eos-s3/btn_counter/Makefile

@@ -1,14 +1,19 @@
-mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
-current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
-TOP:=top
-VERILOG:=btn_counter.v
-DEVICE := ql-eos-s3
-PARTNAME := PD64
-PCF:=chandalar.pcf
-
 ifdef F4PGA_USE_DEPRECATED
 all:
-	ql_symbiflow -compile -d ${DEVICE} -P ${PARTNAME} -v ${VERILOG} -t ${TOP} -p ${PCF}
+# -d: Device
+# -P: Part name
+# -v: Verilog source
+# -t: Top
+# -p: PCF Constrains
+	ql_symbiflow -compile \
+	  -d ql-eos-s3 \
+	  -P PD64 \
+	  -v btn_counter.v \
+	  -t top \
+	  -p chandalar.pcf \
+	  -dump openocd \
+	  -dump header \
+	  -dump binary
 else
 all:
 	f4pga -vvv build --flow ./flow.json

eos-s3/btn_counter/README.rst

@@ -7,6 +7,4 @@ counter example, run the following command:
 .. code-block:: bash
    :name: eos-s3-counter
 
-   #FIXME: make sure FPGA_FAM is available and remove env var export
-   export FPGA_FAM=eos-s3
    make -C btn_counter