Hardware
/
f4pga-examples
mirror of https://github.com/chipsalliance/f4pga-examples.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

xc7: Remove the PCF file from linux_litex_demo. 

A pcf file should not be needed as the xdc provides the IO constraints.

Fixes https://github.com/SymbiFlow/symbiflow-examples/issues/235

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
This commit is contained in:
Tim 'mithro' Ansell 2021-12-28 19:40:38 -08:00
parent 140dbd1e3e
commit 2435b39976
2 changed files with 0 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
xc7/linux_litex_demo/Makefile
View File

@ -3,7 +3,6 @@ TOP := top
SOURCES := ${current_dir}/baselitex_arty.v \
${current_dir}/../../third_party/vexriscv-verilog/VexRiscv_Linux.v
PCF := ${current_dir}/arty.pcf
SDC := ${current_dir}/arty.sdc
XDC := ${current_dir}/arty.xdc

86
xc7/linux_litex_demo/arty.pcf
View File

@ -1,86 +0,0 @@
# 100 MHz CLK
set_io clk100 E3
# Reset
set_io cpu_reset C2
# UART
set_io serial_rx A9
set_io serial_tx D10
# LEDs
set_io led[0] H5
set_io led[1] J5
set_io led[2] T9
set_io led[3] T10
# DDRAM
set_io ddram_a[0] R2
set_io ddram_a[1] M6
set_io ddram_a[2] N4
set_io ddram_a[3] T1
set_io ddram_a[4] N6
set_io ddram_a[5] R7
set_io ddram_a[6] V6
set_io ddram_a[7] U7
set_io ddram_a[8] R8
set_io ddram_a[9] V7
set_io ddram_a[10] R6
set_io ddram_a[11] U6
set_io ddram_a[12] T6
set_io ddram_a[13] T8
set_io ddram_ba[0] R1
set_io ddram_ba[1] P4
set_io ddram_ba[2] P2
set_io ddram_ras_n P3
set_io ddram_cas_n M4
set_io ddram_we_n P5
set_io ddram_cs_n U8
set_io ddram_dm[0] L1
set_io ddram_dm[1] U1
set_io ddram_dq[0] K5
set_io ddram_dq[1] L3
set_io ddram_dq[2] K3
set_io ddram_dq[3] L6
set_io ddram_dq[4] M3
set_io ddram_dq[5] M1
set_io ddram_dq[6] L4
set_io ddram_dq[7] M2
set_io ddram_dq[8] V4
set_io ddram_dq[9] T5
set_io ddram_dq[10] U4
set_io ddram_dq[11] V5
set_io ddram_dq[12] V1
set_io ddram_dq[13] T3
set_io ddram_dq[14] U3
set_io ddram_dq[15] R3
set_io ddram_dqs_p[0] N2
set_io ddram_dqs_p[1] U2
set_io ddram_dqs_n[0] N1
set_io ddram_dqs_n[1] V2
set_io ddram_clk_p U9
set_io ddram_clk_n V9
set_io ddram_cke N5
set_io ddram_odt R5
set_io ddram_reset_n K6
# ETHERNET
set_io eth_ref_clk G18
set_io eth_clocks_tx H16
set_io eth_clocks_rx F15
set_io eth_rst_n C16
set_io eth_mdio K13
set_io eth_mdc F16
set_io eth_rx_dv G16
set_io eth_rx_er C17
set_io eth_rx_data[0] D18
set_io eth_rx_data[1] E17
set_io eth_rx_data[2] E18
set_io eth_rx_data[3] G17
set_io eth_tx_en H15
set_io eth_tx_data[0] H14
set_io eth_tx_data[1] J14
set_io eth_tx_data[2] J13
set_io eth_tx_data[3] H17
set_io eth_col D17
set_io eth_crs G14