docs: use extlinks instead of raw refs

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

docs/customizing-makefiles.rst

@@ -72,7 +72,7 @@ above to a ``.sv``.
 
 .. note::
 
-   As of this writing, F4PGAw only offers full support for Verilog by default.
+   As of this writing, F4PGA only offers full support for Verilog by default.
    SystemVerilog can also be run through the toolchain but more complicated
    designs may not be fully supported.
 
@@ -111,7 +111,7 @@ A Note on the example designs use of ifeq/else ifeq blocks
 
 If you look at the Makefiles from the example designs within F4PGA
 (i.e. counter test, Picosoc, etc.), you will find an ifeq else ifeq block. The following snippet
-is from lines 9-39 of `the Makefile from counter test <https://github.com/chipsalliance/f4pga-examples/blob/master/xc7/counter_test/Makefile>`_:
+is from lines 9-39 of :gh:`the Makefile from counter test <chipsalliance/f4pga-examples/blob/master/xc7/counter_test/Makefile>`:
 
 
 .. code-block:: bash

docs/index.rst

@@ -1,9 +1,9 @@
 Welcome to F4PGA examples!
 ==========================
 
-This guide explains how to get started with F4PGA and build example designs
-from the `F4PGA Examples <https://github.com/chipsalliance/f4pga-examples>`_
-GitHub repository. It currently focuses on the following FPGA families:
+This guide explains how to get started with F4PGA and build example designs from the :gh:`F4PGA Examples <chipsalliance/f4pga-examples>`
+GitHub repository.
+It currently focuses on the following FPGA families:
 
 - Artix-7 from Xilinx,
 - EOS S3 from QuickLogic.

docs/project-f.rst

@@ -2,17 +2,15 @@ Running Project F designs in F4PGA
 ==================================
 
 .. warning::
-   F4PGA does not currently support the MMCME2_BASE primitive--a key commponent in Project F's 
-   clock_gen_480p module and all designs involving video output. 
-   As such, all of the designs in project F that require a display (all designs in FPGA graphics) will
-   fail when run through the toolchain. Only the designs in 
-   `Hello Arty <https://github.com/projf/projf-explore/tree/master/hello/hello-arty>`_ are currently 
-   officially supported. To track the progress of the MMCME2_BASE see issue 
-   `#153 <https://github.com/chipsalliance/f4pga-examples/issues/153>`_ in f4pga examples and 
-   issue `#2246 <https://github.com/f4pga/f4pga-arch-defs/issues/2246>`_ in arch-defs.
-   One user was able to successfully run most of the display designs in project F by replacing the
-   MMCM in clock_gen_480p.sv with a PLLE2_ADV. For details on that see issue 
-   `#180 <https://github.com/chipsalliance/f4pga-examples/issues/180>`_ in f4pga-examples.
+   F4PGA does not currently support the MMCME2_BASE primitive--a key commponent in Project F's clock_gen_480p module
+   and all designs involving video output.
+   As such, all of the designs in project F that require a display (all designs in FPGA graphics) will fail when run
+   through the toolchain. Only the designs in :gh:`Hello Arty <projf/projf-explore/tree/master/hello/hello-arty>` are
+   currently officially supported.
+   To track the progress of the MMCME2_BASE see :ghissue:`153` and issue :gh:`chipsalliance/f4pga-arch-defs#2246 <chipsalliance/f4pga-arch-defs/issues/2246>`.
+   One user was able to successfully run most of the display designs in project F by replacing the MMCM in
+   ``clock_gen_480p.sv`` with a PLLE2_ADV.
+   For details on that see :ghissue:`180` in f4pga-examples.
 
 Project F is an amazing repository containing many high quality FPGA example designs that show
 some of the more impressive things you can do with an FPGA. You can find detailed documentation on
@@ -38,8 +36,8 @@ For example, to build the first design in project F's hello ary designs:
 
    TARGET="arty_35" make -C projf-makefiles/hello/hello-arty/A
 
-To download the bitstream to the board run ``make download``. For example to download the first design from 
-hello arty, run the following in F4PGA root directory:
+To download the bitstream to the board run ``make download``.
+For example, to download the first design from hello arty, run the following in F4PGA's root directory:
 
 .. code-block:: bash
 

xc7/linux_litex_demo/README.rst

@@ -1,12 +1,13 @@
 Linux LiteX demo
 ~~~~~~~~~~~~~~~~
 
-This example design features a Linux-capable SoC based around VexRiscv soft
-CPU. It also includes DDR and Ethernet controllers. To build the litex example,
-run the following commands:
-
-To build the linux-litex-demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:
+This example design features a Linux-capable SoC based around VexRiscv soft CPU.
+It also includes DDR and Ethernet controllers.
+To build the litex example, run the following commands:
 
+To build the linux-litex-demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series
+FPGAs.
+Then, depending on your hardware, run:
 
 .. code-block:: bash
    :name: example-litex-a35t-group
@@ -35,8 +36,7 @@ Now you can upload the design with:
    The LiteX design is provided with an Ethernet module that uses the ``192.168.100.100/24``
    IPv4 address that needs to be set on your network interface.
 
-   You may find these information useful to correctly setup the network interface:
-   https://github.com/timvideos/litex-buildenv/wiki/Networking
+   You may find these information useful to correctly setup the network interface: :gh:`timvideos/litex-buildenv/wiki/Networking`.
 
 You should observe the following line in the OpenOCD output: