Hardware
/
f4pga-examples
mirror of https://github.com/chipsalliance/f4pga-examples.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litex_sata_demo/readme: use a list and role 'gh' 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-09-10 02:39:35 +02:00
parent 8a62c19482
commit 4f49af347d
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
xc7/litex_sata_demo/README.rst
View File

@ -24,13 +24,13 @@ At completion, the bitstreams are located in the build directory:
.. NOTE:: .. NOTE::
To generate the source files for this test, the following packages were used: To generate the source files for this test, the following packages were used:
``enjoy-digital/litex@95b310ee0f0d9e78e00eb32b71324b25265da4f4``,
``enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7``, * :gh:`LiteX <enjoy-digital/litex>` @95b310ee0f0d9e78e00eb32b71324b25265da4f4
``enjoy-digital/litedram@2c60861929a317af697267d6219da43d10dcf1fa``, * :gh:`LiteSATA <enjoy-digital/litesata>` @fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7
``enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91``, * :gh:`LiteDRAM <enjoy-digital/litedram>` @2c60861929a317af697267d6219da43d10dcf1fa
``litex-hub/litex-boards@ea58ef94a784308ae024a1d201d603bc8459a590``, * :gh:`LiteICLink <enjoy-digital/liteiclink>` @0980a7cf4ffcb0b69a84fa0343a66180408b2a91
and * :gh:`LiteX Boards <litex-hub/litex-boards>` @ea58ef94a784308ae024a1d201d603bc8459a590
``m-labs/migen@c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5``. * :gh:`migen <m-labs/migen>` @c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5
.. NOTE:: .. NOTE::
The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow. The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow.