Merge pull request #111 from antmicro/litex-example

Litex example

.github/scripts/build-examples.sh

@@ -47,7 +47,7 @@ shift
 
 examples="$@"
 if [ "$fpga_family" == "xc7" -a -z "$examples" ]; then
-    examples="counter picosoc litex_linux"
+    examples="counter picosoc litex litex_linux"
 elif [ "$fpga_family" == "eos-s3" -a -z "$examples" ]; then
     examples="counter"
 fi
@@ -66,6 +66,12 @@ if [ "$fpga_family" = "xc7" ]; then
             "picosoc")
                 snippets="${snippets} xc7/picosoc_demo/README.rst:example-picosoc-*-group"
                 ;;
+            "litex")
+                tuttest_exec xc7/litex_demo/README.rst example-litex-dir
+                tuttest_exec xc7/litex_demo/README.rst example-litex-req
+                tuttest_exec xc7/litex_demo/README.rst example-litex_picorv32-*-group
+                tuttest_exec xc7/litex_demo/README.rst example-litex_vexriscv-*-group
+                ;;
             "litex_linux")
                 snippets="${snippets} xc7/linux_litex_demo/README.rst:example-litex-deps,example-litex-*-group"
                 ;;

.github/workflows/sphinx-tuttest.yml

@@ -40,6 +40,15 @@ jobs:
           - {fpga-fam: "xc7",    os: "debian", os-version: "bullseye", example: "picosoc"}
           - {fpga-fam: "xc7",    os: "debian", os-version: "sid",      example: "picosoc"}
 
+          - {fpga-fam: "xc7",    os: "ubuntu", os-version: "xenial",   example: "litex"}
+          - {fpga-fam: "xc7",    os: "ubuntu", os-version: "bionic",   example: "litex"}
+          - {fpga-fam: "xc7",    os: "ubuntu", os-version: "focal",    example: "litex"}
+          - {fpga-fam: "xc7",    os: "centos", os-version: "7",        example: "litex"}
+          - {fpga-fam: "xc7",    os: "centos", os-version: "8",        example: "litex"}
+          - {fpga-fam: "xc7",    os: "debian", os-version: "buster",   example: "litex"}
+          - {fpga-fam: "xc7",    os: "debian", os-version: "bullseye", example: "litex"}
+          - {fpga-fam: "xc7",    os: "debian", os-version: "sid",      example: "litex"}
+
           - {fpga-fam: "xc7",    os: "ubuntu", os-version: "xenial",   example: "litex_linux"}
           - {fpga-fam: "xc7",    os: "ubuntu", os-version: "bionic",   example: "litex_linux"}
           - {fpga-fam: "xc7",    os: "ubuntu", os-version: "focal",    example: "litex_linux"}
@@ -48,6 +57,7 @@ jobs:
           - {fpga-fam: "xc7",    os: "debian", os-version: "buster",   example: "litex_linux"}
           - {fpga-fam: "xc7",    os: "debian", os-version: "bullseye", example: "litex_linux"}
           - {fpga-fam: "xc7",    os: "debian", os-version: "sid",      example: "litex_linux"}
+
     env:
       LANG: "en_US.UTF-8"
       DEBIAN_FRONTEND: "noninteractive"

docs/building-examples.rst

@@ -64,6 +64,9 @@ Enter the directory that contains examples for Xilinx 7-Series FPGAs:
 .. jinja:: xc7_picosoc_demo
    :file: templates/example.jinja
 
+.. jinja:: xc7_litex_demo
+   :file: templates/example.jinja
+
 .. jinja:: xc7_linux_litex_demo
    :file: templates/example.jinja
 

xc7/README.rst

@@ -3,6 +3,7 @@ SymbiFlow Toolchain Examples for Xilinx 7 Series
 
 #. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
 #. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
+#. ``litex`` - Series of `LiteX-based <https://github.com/enjoy-digital/litex>`__ designs, that feature different CPU types and LiteX modules.
 #. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
 
 The Linux images for the ``linux_litex`` example can be built following the `linux on litex vexriscv <https://github.com/litex-hub/linux-on-litex-vexriscv>`__ instructions.

xc7/environment.yml

@@ -8,6 +8,7 @@ dependencies:
   - litex-hub::prjxray-db=0.0_248_g2e51ad3=20210312_125539
   - litex-hub::vtr-optimized=8.0.0_3445_ga806b1609=20210312_125539
   - litex-hub::yosys=0.9_5266_g0fb4224e=20210301_104249_py37
+  - litex-hub::gcc-riscv64-elf-newlib=9.2.0=20201119_154229
   - make
   - lxml
   - simplejson

xc7/linux_litex_demo/README.rst

@@ -5,20 +5,6 @@ This example design features a Linux-capable SoC based around VexRiscv soft
 CPU. It also includes DDR and Ethernet controllers. To build the litex example,
 run the following commands:
 
-.. code-block:: bash
-   :name: example-litex-deps
-
-   wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-   chmod +x litex_setup.py
-   ./litex_setup.py init
-   ./litex_setup.py install
-   wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-   tar -xf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-   export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
-   cd litex-boards/litex_boards/targets
-   ./digilent_arty.py --toolchain symbiflow --cpu-type vexriscv --build
-   cd -
-
 To build the linux-litex-demo example, depending on your hardware, run:
 
 .. code-block:: bash

xc7/litex_demo/.gitignore

@@ -0,0 +1,3 @@
+# Litex directory
+
+src

xc7/litex_demo/README.rst

@@ -0,0 +1,71 @@
+LiteX demo
+~~~~~~~~~~
+
+This example design features a LiteX+<CPU variant>-based SoC. It also includes DDR
+controller. First, enter this example's directory:
+
+.. code-block:: bash
+   :name: example-litex-dir
+
+   cd litex_demo
+
+Install the litex dependencies with the following:
+
+.. code-block:: bash
+   :name: example-litex-req
+
+   pip install -r requirements.txt
+
+There are multiple CPU types supported, choose one from the below commands to generate the design and build it.
+
+**Picorv32**
+
+.. code-block:: bash
+   :name: example-litex_picorv32-a35t-group
+
+   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --variant a7-35 --build
+
+.. code-block:: bash
+   :name: example-litex_picorv32-a100t-group
+
+   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --variant a7-100 --build
+
+**VexRiscv**
+
+.. code-block:: bash
+   :name: example-litex_vexriscv-a35t-group
+
+   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --variant a7-35 --build
+
+.. code-block:: bash
+   :name: example-litex_vexriscv-a100t-group
+
+   ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --variant a7-100 --build
+
+Depending on which board and CPU-type you selected, the bitstream is loacted in:
+
+.. code-block:: bash
+
+   cd build/<cpu-type>/<board>/gateware
+
+Now you can upload the design with:
+
+.. code-block:: bash
+
+   openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
+
+.. note::
+
+   This example uses baud rate of ``115200`` by default.
+
+You should observe the following line in the OpenOCD output
+
+.. code-block:: bash
+
+   Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
+
+In the ``picocom`` terminal, you should observe the following output:
+
+.. image:: ../../docs/images/litex-picorv32-console.gif
+   :align: center
+   :width: 80%

xc7/litex_demo/requirements.txt

@@ -0,0 +1,33 @@
+# LiteX
+-e git+https://github.com/enjoy-digital/litex@afbac26e8015fdca70e7b2bc1477db31f7860c38#egg=litex
+-e git+https://github.com/enjoy-digital/litedram@103072c68a2e3ec9c81f198e50e5427e5780580c#egg=litedram
+-e git+https://github.com/enjoy-digital/liteeth@617400fe9e5b902e6bfd39a7c32ef5b255bc10c0#egg=liteeth
+-e git+https://github.com/enjoy-digital/liteiclink@8b29505096406d242685bf71b16a0ce4e4be54aa#egg=liteiclink
+-e git+https://github.com/enjoy-digital/litejesd204b@7228931a2697ba2694e563028acc399c57b88dbb#egg=litejesd204b
+-e git+https://github.com/enjoy-digital/litepcie@579c5b423b2442fd224853a448e66189b68202d0#egg=litepcie
+-e git+https://github.com/enjoy-digital/litesata@a9a4c5845a43bdfb81570bfd2b8869c7f4e18350#egg=litesata
+-e git+https://github.com/enjoy-digital/litescope@f78400aa29cb328641fb28e1aba097afcb25c16b#egg=litescope
+-e git+https://github.com/enjoy-digital/litesdcard@0cb5ab5bab0bba9c3f3c900837bd39e745465aa2#egg=litesdcard
+-e git+https://github.com/enjoy-digital/litevideo@41f30143075ece3fff5c33a332ed067d1837cbb3#egg=litevideo
+-e git+https://github.com/litex-hub/litehyperbus@5282d5167c4c91984b614febdb062450b26aec52#egg=litehyperbus
+-e git+https://github.com/litex-hub/litespi@024326c423b053e4cff9a30932c7b38fe38d252d#egg=litespi
+-e git+https://github.com/litex-hub/litex-boards@e1f9fd1a25de353ca7682a745955a5fc4db9c81d#egg=litex_boards
+
+# Migen and nMigen
+-e git+https://github.com/m-labs/migen@9a37a588121d9ba72e723bc6eeeb4b0195d7b98c#egg=migen
+-e git+https://github.com/nmigen/nmigen@b466b724fe9f62140062afc9ecde9a920a261487#egg=nmigen
+
+# Pythondata for different CPU types
+-e git+https://github.com/litex-hub/pythondata-cpu-blackparrot@4264d9b0ee43dbb04a94260a6cf9063202996537#egg=pythondata_cpu_blackparrot
+-e git+https://github.com/litex-hub/pythondata-cpu-cv32e40p@b8fe3c41bfe87eb382449bcbf0f7f0e061d45e08#egg=pythondata_cpu_cv32e40p
+-e git+https://github.com/litex-hub/pythondata-cpu-lm32@63440000de23714f602637f772559980c0f6678e#egg=pythondata_cpu_lm32
+-e git+https://github.com/litex-hub/pythondata-cpu-microwatt@ba76652320e9dc23d9b2c64a62d0a752c870a215#egg=pythondata_cpu_microwatt
+-e git+https://github.com/litex-hub/pythondata-cpu-minerva@2a69b7f3051df7a59d417b08bde963b9e6b8396b#egg=pythondata_cpu_minerva
+-e git+https://github.com/litex-hub/pythondata-cpu-mor1kx@ff018922b07fd0e55d92f0d9ba58ee4d0e0d8a5d#egg=pythondata_cpu_mor1kx
+-e git+https://github.com/litex-hub/pythondata-cpu-picorv32@8bdce32bf6db95df397ea8f9904e38ae9cae5641#egg=pythondata_cpu_picorv32
+-e git+https://github.com/litex-hub/pythondata-cpu-rocket@e5bbab953c9265e351600a783be70065708a1c40#egg=pythondata_cpu_rocket
+-e git+https://github.com/litex-hub/pythondata-cpu-serv@8976da102013beeb07d30f7b9af7611bcfdf5a7f#egg=pythondata_cpu_serv
+-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv
+-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv-smp@c7cf25663a90a00772d1fc8f55028e423cbde770#egg=pythondata_cpu_vexriscv_smp
+-e git+https://github.com/litex-hub/pythondata-misc-tapcfg@4befb8bc3dd0bc30e7554d0d30a5f99c9bec0fad#egg=pythondata_misc_tapcfg
+-e git+https://github.com/litex-hub/pythondata-software-compiler_rt@fcb03245613ccf3079cc833a701f13d0beaae09d#egg=pythondata_software_compiler_rt