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Merge pull request #84 from antmicro/add-zynq-counter-test 

Add zynq counter test
This commit is contained in:
Tomasz Michalak 2020-12-15 13:52:30 +01:00 committed by GitHub
parent 0f2fb6a472 8ae95b0d8d
commit 5a550c64bd
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GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 99 additions and 35 deletions
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1
xc7/README.rst
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@ -79,6 +79,7 @@ To build the counter example, run any or all of the following commands:
pushd xc7/counter_test && TARGET="arty_35" make && popd
pushd xc7/counter_test && TARGET="arty_100" make && popd
pushd xc7/counter_test && TARGET="basys3" make && popd
pushd xc7/counter_test && TARGET="zybo" make && popd
To build the picosoc example, run the following commands:

22
xc7/counter_test/Makefile
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@ -4,21 +4,27 @@ TOP:=top
VERILOG:=${current_dir}/counter.v
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
SDC:=${current_dir}/counter.sdc
BUILDDIR:=build
ifeq ($(TARGET),arty_35)
PARTNAME := xc7a35tcsg324-1
PCF:=${current_dir}/arty.pcf
XDC:=${current_dir}/arty.xdc
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
else ifeq ($(TARGET),arty_100)
PARTNAME:= xc7a100tcsg324-1
PCF:=${current_dir}/arty.pcf
XDC:=${current_dir}/arty.xdc
DEVICE:= xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
else ifeq ($(TARGET),zybo)
PARTNAME:= xc7z010clg400-1
XDC:=${current_dir}/zybo.xdc
DEVICE:= xc7z010_test
BITSTREAM_DEVICE:= zynq7
BOARD_BUILDDIR := ${BUILDDIR}/zybo
VERILOG:=${current_dir}/counter_zynq.v
else
PARTNAME:= xc7a35tcpg236-1
PCF:=${current_dir}/basys3.pcf
XDC:=${current_dir}/basys3.xdc
BOARD_BUILDDIR := ${BUILDDIR}/basys3
endif
@ -28,16 +34,16 @@ ${BOARD_BUILDDIR}:
mkdir -p ${BOARD_BUILDDIR}
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
cd ${BOARD_BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}

12
xc7/counter_test/arty.pcf
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@ -1,12 +0,0 @@
# 100 MHz CLK
set_io clk E3
# UART
set_io rx A9
set_io tx D10
# LEDs
set_io led[0] H5
set_io led[1] J5
set_io led[2] T9
set_io led[3] T10

16
xc7/counter_test/arty.xdc Normal file
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@ -0,0 +1,16 @@
# Clock pin
set_property PACKAGE_PIN E3 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property PACKAGE_PIN H5 [get_ports {led[0]}]
set_property PACKAGE_PIN J5 [get_ports {led[1]}]
set_property PACKAGE_PIN T9 [get_ports {led[2]}]
set_property PACKAGE_PIN T10 [get_ports {led[3]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 10.0 [get_ports {clk}]

11
xc7/counter_test/basys3.pcf
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@ -1,11 +0,0 @@
# basys3 100 MHz CLK
set_io clk W5
set_io tx A18
set_io rx B18
# out[0:15] correspond with LD0-LD15 on the basys3
set_io led[0] U16
set_io led[1] E19
set_io led[2] U19
set_io led[3] V19

16
xc7/counter_test/basys3.xdc Normal file
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@ -0,0 +1,16 @@
# Clock pin
set_property PACKAGE_PIN W5 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 10.0 [get_ports {clk}]

1
xc7/counter_test/counter.sdc
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@ -1 +0,0 @@
create_clock -period 10 bufg

3
xc7/counter_test/counter.v
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@ -1,7 +1,5 @@
module top (
input clk,
input rx,
output tx,
output [3:0] led
);
@ -18,5 +16,4 @@ module top (
end
assign led[3:0] = counter >> LOG2DELAY;
assign tx = rx;
endmodule

36
xc7/counter_test/counter_zynq.v Normal file
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@ -0,0 +1,36 @@
module top(
input wire clk,
output wire [3:0] led
);
wire [63:0] emio_gpio_o;
wire [63:0] emio_gpio_t;
wire [63:0] emio_gpio_i;
wire clk_bufg;
BUFG BUFG(.I(clk), .O(clk_bufg));
wire en_counter = ~emio_gpio_o[0];
wire count_direction = ~emio_gpio_o[1];
reg [31:0] counter = 0;
always @(posedge clk_bufg) begin
if (en_counter)
if (count_direction)
counter <= counter + 1;
else
counter <= counter - 1;
end
assign led = counter[27:24];
// The PS7
(* KEEP, DONT_TOUCH *)
PS7 PS7(
.EMIOGPIOO (emio_gpio_o),
.EMIOGPIOTN (emio_gpio_t),
.EMIOGPIOI (emio_gpio_i),
);
endmodule

16
xc7/counter_test/zybo.xdc Normal file
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@ -0,0 +1,16 @@
# Clock pin
set_property LOC K17 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property LOC M14 [get_ports {led[0]}]
set_property LOC M15 [get_ports {led[1]}]
set_property LOC G14 [get_ports {led[2]}]
set_property LOC D18 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 8.0 [get_ports {clk}]