Add counter test sources

Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>

counter_test/Makefile

@@ -0,0 +1,36 @@
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
+TOP:=top
+VERILOG:=${current_dir}/counter_basys3.v
+PARTNAME:= xc7a35tcpg236-1
+DEVICE  := xc7a50t_test
+BITSTREAM_DEVICE := artix7
+PCF=${current_dir}/basys3.pcf
+BUILDDIR:=build
+
+all: ${BUILDDIR}/${TOP}.bit
+
+${BUILDDIR}:
+	mkdir ${BUILDDIR}
+
+${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
+	cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}
+
+${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
+	cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
+	cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME}
+
+${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
+	cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
+	cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.bit: ${BUILDDIR}/${TOP}.fasm
+	cd ${BUILDDIR} && write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
+
+clean:
+	rm -rf ${BUILDDIR}
+

counter_test/basys3.pcf

@@ -0,0 +1,41 @@
+# basys3 100 MHz CLK
+set_io clk W5
+
+set_io tx A18
+set_io rx B18
+#
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_io sw[0] V17
+set_io sw[1] V16
+set_io sw[2] W16
+set_io sw[3] W17
+set_io sw[4] W15
+set_io sw[5] V15
+set_io sw[6] W14
+set_io sw[7] W13
+set_io sw[8] V2
+set_io sw[9] T3
+set_io sw[10] T2
+set_io sw[11] R3
+set_io sw[12] W2
+set_io sw[13] U1
+set_io sw[14] T1
+set_io sw[15] R2
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_io led[0] U16
+set_io led[1] E19
+set_io led[2] U19
+set_io led[3] V19
+set_io led[4] W18
+set_io led[5] U15
+set_io led[6] U14
+set_io led[7] V14
+set_io led[8] V13
+set_io led[9] V3
+set_io led[10] W3
+set_io led[11] U3
+set_io led[12] P3
+set_io led[13] N3
+set_io led[14] P1
+set_io led[15] L1

counter_test/counter_basys3.v

@@ -0,0 +1,25 @@
+module top (
+    input  clk,
+    input rx,
+    output tx,
+    input [15:0] sw,
+    output [15:0] led
+);
+
+    localparam BITS = 4;
+    localparam LOG2DELAY = 22;
+
+    wire bufg;
+    BUFG bufgctrl(.I(clk), .O(bufg));
+
+    reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+    always @(posedge bufg) begin
+        counter <= counter + 1;
+    end
+
+    assign led[3:0] = counter >> LOG2DELAY;
+    assign led[14:4] = sw[14:4];
+    assign tx = rx;
+    assign led[15] = ^sw;
+endmodule

counter_test/requirements.txt

@@ -0,0 +1,5 @@
+lxml
+simplejson
+intervaltree
+python-constraint
+git+https://github.com/symbiflow/fasm