Added explanation of symbiflow commands
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
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Joshua Fife
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@ -78,7 +78,7 @@ design using the following syntax:
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<HDL language> := ${current_dir}/<HDL file 1> \
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${current_dir}/<HDL file 2>\
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${current_dir}/<HDL file 2> \
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${current_dir}/<HDL file 3> \
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@ -285,7 +285,12 @@ snippets show the differences and the areas that will need to change:
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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Lines 33-37 (running ``symbiflow_write_fasm`` and ``symbiflow_write_bitstream``) typically do not change from design to design.
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Lines 33-37 (running ``symbiflow_write_fasm`` and ``symbiflow_write_bitstream``) typically do
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not change within the makefile from design to design.
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If you would like to learn more about these commands or if you are using methods other than a
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makefile to build and compile your designs (such as python or bash scripts) take a look at
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`Understanding Toolchain Commands <understanding-commands.html>`_.
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A Note on the example designs use of ifeq/else ifeq blocks
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-------------------------------------------------------------
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@ -15,6 +15,7 @@ Follow this guide to:
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example designs onto the devboard of your choice.
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- compile and run :doc:`your own designs<personal-designs>` using the Symbiflow toolchain.
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- :doc:`customize the Makefile<customizing-makefiles>` for your own designs.
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- gain valuable information about `Understanding Toolchain Commands in Symbiflow <understanding-commands.html>`_
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About SymbiFlow
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@ -37,3 +38,4 @@ currently targeting chips from multiple vendors, e.g.:
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running-examples
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personal-designs
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customizing-makefiles
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understanding-commands
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@ -72,7 +72,9 @@ provided, although more complicated designs written in SystemVerilog may not bui
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Yosys. Use whichever method you prefer and add your design files to the directory of choice.
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If you are using the provided Makefiles to build your design, the top level module in your HDL
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code should be declared as ``module top (...``. Failure to do so will result in an error from
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symbiflow_synth stating something similar to ``ERROR: Module 'top' not found!``
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symbiflow_synth stating something similar to ``ERROR: Module 'top' not found!`` If you are using
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your own makefiles or commands you can specify your top level module name using the -t flag in
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symbiflow_synth.
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@ -0,0 +1,163 @@
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Understanding Toolchain Commands
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=================================
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This section provides valuable information on how each of the commands used to compile and build
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designs in Symbiflow work. It is especially helpful for debugging or if you are using methods
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other than a makefile to build your designs, such as a bash or python script.
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The following describes the commands for running each of the steps for a full design flow
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(synthesis, place and route, and generate bitstream) as well as giving a description of the most
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common flags for those commands. If you would like a more detailed break down of how the design
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flow for Symbiflow works take a look at the
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`FPGA Design Flow page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/design-flow.html>`_.
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.. note::
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Files created by the synthesis, implementation, and bitstream generation will be dumped into
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the directory from which the command is run. To keep all of the files generated by the toolchain
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separate from your design files you might consider running the toolchain commands in a separate
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directory from your design files.
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Synthesis
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----------
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To synthesize your designs run the ``symbiflow_synth`` command. The command has the following flags:
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+------+------------------------------------------------------+
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| Flag | Argument |
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+======+======================================================+
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| -t | Defines the name for the top level module |
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+------+------------------------------------------------------+
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| -v | A list of verilog/systemVerilog files for the design |
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+------+------------------------------------------------------+
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| -d | FPGA family (i.e. artix7 or zynq7) |
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+------+------------------------------------------------------+
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| -p | The part number for the FPGA (i.e xc7a35tcsg324-1) |
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+------+------------------------------------------------------+
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| -x | Optional command: path to xdc files for design |
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+------+------------------------------------------------------+
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An example of how to run synthesis on a design containing two separate
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verilog HDL files is bellow. The design is built for a basys3 board which comes from the artix7
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family and uses the xc7a35tcpg236-1 chip.
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.. code-block:: bash
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symbiflow_synth -t top -v file1.v file2.v -d artix7 -p xc7a35tcpg236-1 -x design_constraint.xdc
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The symbiflow_synth command synthesizes your design using the Yosys open source tool and generates
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an .eblif file (the name of the file is the name for your top level module as defined by the -t
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option), some verilog files that describe the gate level design for your project, and a log
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file. For more information on Yosys and its relation to symbiflow follow
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`this link <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/yosys.html>`_.
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.. note::
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The build files generated by the toolchain (for example .eblif from synthesis, .net from packing, .bit
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from generate bitstream) are named using the top module specified in symbiflow_synth. For
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example if you specified ``switch_top`` as the top level module during synthesis using the ``-t``
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flag, the build files generated by the toolchain would be named switch_top.eblif, switch_top.net,
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etc.
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Implementation/Place and Route
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-------------------------------
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The steps for implementing a design are internally handled by the open source VPR
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(Versatile Place and Route) tool. For more information go to
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`the Symbiflow VPR page <https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/vpr/index.html>`_.
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Pack
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+++++
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Packing is run by the ``symbiflow_pack`` command and generates several files containing
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a pin usage report, a timing report, a log file, and a netlist. The various flags for the
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pack command are as follows:
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+------+--------------------------------------------------------------------+
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| Flag | Argument |
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+======+====================================================================+
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| -e | Path to .eblif file generated by synthesis |
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+------+--------------------------------------------------------------------+
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| -d | Fabric specification for the board (i.e. xc7a100t_test) |
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+------+--------------------------------------------------------------------+
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| -s | Optional: SDC file path |
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+------+--------------------------------------------------------------------+
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Note that the -d option from the pack step (defining the fabric specification) is different
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from the -d from synthesis (defining the FPGA family).
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The following example runs packing on the basys3 board:
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.. code-block:: bash
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symbiflow_pack -e top.eblif -d xc7a35t_test
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Place
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++++++
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Placement is run using ``symbiflow_place`` which utilizes the following flags:
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+------+----------------------------------------------------+
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| Flag | Argument |
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+======+====================================================+
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| -e | Path to .eblif file generated by synthesis |
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+------+----------------------------------------------------+
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| -d | Fabric specification (xc7a50t_tes) |
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+------+----------------------------------------------------+
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| -p | Optional: PCF file path |
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+------+----------------------------------------------------+
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| -n | Path to the .net file generated by pack step |
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+------+----------------------------------------------------+
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| -P | The part number for the FPGA (i.e xc7a35tcsg324-1) |
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+------+----------------------------------------------------+
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| -s | Optional: SDC file path |
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+------+----------------------------------------------------+
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For the basys3:
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.. code-block:: bash
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symbiflow_pack -e top.eblif -d xc7a35t_test -p design.pcf -n top.net -P xc7a35tcpg236-1 -s design.sdc
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Route
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++++++
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Routing produces several timing reports as well as a post routing netlist and log file.
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``symbiflow_route`` uses the -e, -d, and the optional -s flags with the same use cases as in
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placement.
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Generating Bitstream
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----------------------
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Generating the bitstream consists of two steps. First, ``symbiflow_write_fasm`` is run to
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generate the .fasm file. ``symbiflow_write_fasm`` uses the -e and -d flags with the same use
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cases as in placing and routing. Second, ``symbiflow_write_bitstream`` is run. The
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``symbiflow_write_bitstream`` command has the following flags:
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+------+-------------------------------------------------------+
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| Flag | Argument |
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+======+=======================================================+
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| -d | FPGA family (i.e. artix7 or zynq7) |
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+------+-------------------------------------------------------+
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| -f | The name of the .fasm file generated in by write_fasm |
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+------+-------------------------------------------------------+
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| -p | The FPGA part number (i.e xc7a35tcsg324-1) |
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+------+-------------------------------------------------------+
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| -b | Name of the file to write the bitstream to |
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+------+-------------------------------------------------------+
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Notice that the specification for the part number is a lowercase ``-p`` instead of a capital ``-P``
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as in the placement step. ``-d`` in bitstream also defines the FPGA family instead of the fabric as
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in write_fasm step.
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The following example generates a bitstream file named example.bit:
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.. code-block:: bash
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symbiflow_write_fasm -e top.eblif -d xc7a50t_test
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symbiflow_write_bitstream -d artix7 -f top.fasm -p xc7a35tcpg236-1 -b example.bit
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