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xc7: add picorv32 and vexriscv litex example

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Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Filip Kokosinski 2020-12-15 10:06:43 +01:00 committed by Alessandro Comodi
parent ca3f9ce817
commit 63d392b21c
8 changed files with 283 additions and 1 deletions
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8
.github/scripts/build-examples.sh vendored
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@ -47,7 +47,7 @@ shift
examples="$@"
if [ "$fpga_family" == "xc7" -a -z "$examples" ]; then
examples="counter picosoc litex_linux"
examples="counter picosoc litex litex_linux"
elif [ "$fpga_family" == "eos-s3" -a -z "$examples" ]; then
examples="counter"
fi
@ -66,6 +66,12 @@ if [ "$fpga_family" = "xc7" ]; then
"picosoc")
snippets="${snippets} xc7/picosoc_demo/README.rst:example-picosoc-*-group"
;;
"litex")
tuttest_exec xc7/litex_demo/README.rst example-litex-dir
tuttest_exec xc7/litex_demo/README.rst example-litex-req
tuttest_exec xc7/litex_demo/README.rst example-litex_picorv32-*-group
tuttest_exec xc7/litex_demo/README.rst example-litex_vexriscv-*-group
;;
"litex_linux")
snippets="${snippets} xc7/linux_litex_demo/README.rst:example-litex-deps,example-litex-*-group"
;;

10
.github/workflows/sphinx-tuttest.yml vendored
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@ -40,6 +40,15 @@ jobs:
- {fpga-fam: "xc7", os: "debian", os-version: "bullseye", example: "picosoc"}
- {fpga-fam: "xc7", os: "debian", os-version: "sid", example: "picosoc"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "xenial", example: "litex"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "bionic", example: "litex"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "focal", example: "litex"}
- {fpga-fam: "xc7", os: "centos", os-version: "7", example: "litex"}
- {fpga-fam: "xc7", os: "centos", os-version: "8", example: "litex"}
- {fpga-fam: "xc7", os: "debian", os-version: "buster", example: "litex"}
- {fpga-fam: "xc7", os: "debian", os-version: "bullseye", example: "litex"}
- {fpga-fam: "xc7", os: "debian", os-version: "sid", example: "litex"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "xenial", example: "litex_linux"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "bionic", example: "litex_linux"}
- {fpga-fam: "xc7", os: "ubuntu", os-version: "focal", example: "litex_linux"}
@ -48,6 +57,7 @@ jobs:
- {fpga-fam: "xc7", os: "debian", os-version: "buster", example: "litex_linux"}
- {fpga-fam: "xc7", os: "debian", os-version: "bullseye", example: "litex_linux"}
- {fpga-fam: "xc7", os: "debian", os-version: "sid", example: "litex_linux"}
env:
LANG: "en_US.UTF-8"
DEBIAN_FRONTEND: "noninteractive"

3
docs/building-examples.rst
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@ -64,6 +64,9 @@ Enter the directory that contains examples for Xilinx 7-Series FPGAs:
.. jinja:: xc7_picosoc_demo
:file: templates/example.jinja
.. jinja:: xc7_litex_demo
:file: templates/example.jinja
.. jinja:: xc7_linux_litex_demo
:file: templates/example.jinja

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3
xc7/litex_demo/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
# Litex directory
src

71
xc7/litex_demo/README.rst Normal file
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@ -0,0 +1,71 @@
LiteX demo
~~~~~~~~~~
This example design features a LiteX+<CPU variant>-based SoC. It also includes DDR
controller. First, enter this example's directory:
.. code-block:: bash
:name: example-litex-dir
cd litex_demo
Install the litex dependencies with the following:
.. code-block:: bash
:name: example-litex-req
pip install -r requirements.txt
There are multiple CPU types supported, choose one from the below commands to generate the design and build it.
**Picorv32**
.. code-block:: bash
:name: example-litex_picorv32-a35t-group
./arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --uart-baudrate=1000000 --output-dir build/picorv32/arty_35 --board-variant a7-35 --build
.. code-block:: bash
:name: example-litex_picorv32-a100t-group
./arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --uart-baudrate=1000000 --output-dir build/picorv32/arty_100 --board-variant a7-100 --build
**VexRiscv**
.. code-block:: bash
:name: example-litex_vexriscv-a35t-group
./arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --uart-baudrate=1000000 --output-dir build/vexriscv/arty_35 --board-variant a7-35 --build
.. code-block:: bash
:name: example-litex_vexriscv-a100t-group
./arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --uart-baudrate=1000000 --output-dir build/vexriscv/arty_100 --board-variant a7-100 --build
Depending on which board and CPU-type you selected, the bitstream is loacted in:
.. code-block:: bash
cd build/<cpu-type>/<board>/gateware
Now you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
.. note::
This example uses baud rate of ``1000000`` by default.
You should observe the following line in the OpenOCD output
.. code-block:: bash
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
In the ``picocom`` terminal, you should observe the following output:
.. image:: ../../docs/images/litex-picorv32-console.gif
:align: center
:width: 80%

156
xc7/litex_demo/arty.py Executable file
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@ -0,0 +1,156 @@
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex.boards.platforms import arty
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(
self,
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
ident_version=True,
board_variant="a7-35",
**kwargs
):
platform = arty.Platform(variant=board_variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--board-variant", default="a7-35", help="Board variant (default: a7-35)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
ident_version = args.no_ident_version,
board_variant = args.board_variant,
**soc_sdram_argdict(args)
)
assert not (args.with_spi_sdcard and args.with_sdcard)
soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()

33
xc7/litex_demo/requirements.txt Normal file
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@ -0,0 +1,33 @@
# LiteX
-e git+https://github.com/enjoy-digital/litex@4092180662ec62cf28b9283a020f1ff7f0892c19#egg=litex
-e git+https://github.com/enjoy-digital/litedram@103072c68a2e3ec9c81f198e50e5427e5780580c#egg=litedram
-e git+https://github.com/enjoy-digital/liteeth@617400fe9e5b902e6bfd39a7c32ef5b255bc10c0#egg=liteeth
-e git+https://github.com/enjoy-digital/liteiclink@8b29505096406d242685bf71b16a0ce4e4be54aa#egg=liteiclink
-e git+https://github.com/enjoy-digital/litejesd204b@7228931a2697ba2694e563028acc399c57b88dbb#egg=litejesd204b
-e git+https://github.com/enjoy-digital/litepcie@579c5b423b2442fd224853a448e66189b68202d0#egg=litepcie
-e git+https://github.com/enjoy-digital/litesata@a9a4c5845a43bdfb81570bfd2b8869c7f4e18350#egg=litesata
-e git+https://github.com/enjoy-digital/litescope@f78400aa29cb328641fb28e1aba097afcb25c16b#egg=litescope
-e git+https://github.com/enjoy-digital/litesdcard@0cb5ab5bab0bba9c3f3c900837bd39e745465aa2#egg=litesdcard
-e git+https://github.com/enjoy-digital/litevideo@41f30143075ece3fff5c33a332ed067d1837cbb3#egg=litevideo
-e git+https://github.com/litex-hub/litehyperbus@5282d5167c4c91984b614febdb062450b26aec52#egg=litehyperbus
-e git+https://github.com/litex-hub/litespi@024326c423b053e4cff9a30932c7b38fe38d252d#egg=litespi
-e git+https://github.com/litex-hub/litex-boards@e1f9fd1a25de353ca7682a745955a5fc4db9c81d#egg=litex_boards
# Migen and nMigen
-e git+https://github.com/m-labs/migen@9a37a588121d9ba72e723bc6eeeb4b0195d7b98c#egg=migen
-e git+https://github.com/nmigen/nmigen@b466b724fe9f62140062afc9ecde9a920a261487#egg=nmigen
# Pythondata for different CPU types
-e git+https://github.com/litex-hub/pythondata-cpu-blackparrot@4264d9b0ee43dbb04a94260a6cf9063202996537#egg=pythondata_cpu_blackparrot
-e git+https://github.com/litex-hub/pythondata-cpu-cv32e40p@b8fe3c41bfe87eb382449bcbf0f7f0e061d45e08#egg=pythondata_cpu_cv32e40p
-e git+https://github.com/litex-hub/pythondata-cpu-lm32@63440000de23714f602637f772559980c0f6678e#egg=pythondata_cpu_lm32
-e git+https://github.com/litex-hub/pythondata-cpu-microwatt@ba76652320e9dc23d9b2c64a62d0a752c870a215#egg=pythondata_cpu_microwatt
-e git+https://github.com/litex-hub/pythondata-cpu-minerva@2a69b7f3051df7a59d417b08bde963b9e6b8396b#egg=pythondata_cpu_minerva
-e git+https://github.com/litex-hub/pythondata-cpu-mor1kx@ff018922b07fd0e55d92f0d9ba58ee4d0e0d8a5d#egg=pythondata_cpu_mor1kx
-e git+https://github.com/litex-hub/pythondata-cpu-picorv32@8bdce32bf6db95df397ea8f9904e38ae9cae5641#egg=pythondata_cpu_picorv32
-e git+https://github.com/litex-hub/pythondata-cpu-rocket@e5bbab953c9265e351600a783be70065708a1c40#egg=pythondata_cpu_rocket
-e git+https://github.com/litex-hub/pythondata-cpu-serv@8976da102013beeb07d30f7b9af7611bcfdf5a7f#egg=pythondata_cpu_serv
-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv
-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv-smp@c7cf25663a90a00772d1fc8f55028e423cbde770#egg=pythondata_cpu_vexriscv_smp
-e git+https://github.com/litex-hub/pythondata-misc-tapcfg@4befb8bc3dd0bc30e7554d0d30a5f99c9bec0fad#egg=pythondata_misc_tapcfg
-e git+https://github.com/litex-hub/pythondata-software-compiler_rt@fcb03245613ccf3079cc833a701f13d0beaae09d#egg=pythondata_software_compiler_rt