Merge pull request #285 from antmicro/umarcor/shields

readme: update shields
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Tomasz Michalak 2022-06-01 08:55:39 +02:00 committed by GitHub
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<p align="center">
<a title="Website" href="https://f4pga.org"><img src="https://img.shields.io/website?longCache=true&style=flat-square&label=f4pga.org&up_color=10cfc9&url=https%3A%2F%2Ff4pga.org%2Findex.html&labelColor=fff"></a><!--
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</p>
# F4PGA examples
<p align="center">
<a title="GitHub Actions" href="https://github.com/chipsalliance/f4pga-examples/actions"><img src="https://img.shields.io/github/workflow/status/chipsalliance/f4pga-examples/Automerge/main?longCache=true&style=flat-square&label=Tests&logo=Github%20Actions&logoColor=fff"></a><!--
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</p>
This repository provides example FPGA designs that can be built using the F4PGA open source toolchain.
These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices.
* Please refer to the [![](https://img.shields.io/website?longCache=true&style=flat-square&label=Documentation%20For%20Users&up_color=231f20&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga-examples.readthedocs.io%2Fen%2Flatest%2Findex.html&labelColor=fff)](https://f4pga-examples.readthedocs.io)
for a proper guide on how to run these examples, as well as instructions on how to build and compile your own HDL designs using
the F4PGA toolchain.
* See [![](https://img.shields.io/website?longCache=true&style=flat-square&label=Documentation%20For%20Developers&up_color=white&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga.readthedocs.io%2Fprojects%2Farch-defs%2Fen%2Flatest%2Findex.html&labelColor=231f20)](https://f4pga.readthedocs.io/projects/arch-defs/)
to contribute on the development of architecture support in F4PGA.
The repository includes:
* [xc7/](./xc7) and [eos-s3/](./eos-s3) - Examples for Xilinx 7-Series and EOS-S3 devices, including:
* Verilog code
* Pin constraints files
* Timing constraints files
* Makefiles for running the F4PGA toolchain
* [docs/](./docs) - Guide on how to get started with F4PGA and build provided examples
* [.github/](./.github) - Directory with CI configuration and scripts
The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets
with [tuttest](https://github.com/antmicro/tuttest).

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F4PGA examples
==============
.. image:: https://github.com/chipsalliance/f4pga-examples/workflows/doc-test/badge.svg?branch=master
:target: https://github.com/chipsalliance/f4pga-examples/actions
.. image:: https://readthedocs.org/projects/f4pga-examples/badge/?version=latest
:target: https://f4pga-examples.readthedocs.io/en/latest/?badge=latest
:alt: Documentation Status
This repository provides example FPGA designs that can be built using the F4PGA open source toolchain.
These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices.
Please refer to the `project documentation <https://f4pga-examples.readthedocs.io>`_ for a proper guide on how to run
these examples as well as instructions on how to build and compile your own HDL designs using the F4PGA toolchain.
The repository includes:
* `xc7/ <./xc7>`_ and `eos-s3/ <./eos-s3>`_ - Examples for Xilinx 7-Series and EOS-S3 devices, including:
* Verilog code
* Pin constraints files
* Timing constraints files
* Makefiles for running the F4PGA toolchain
* `docs/ <./docs>`_ - Guide on how to get started with F4PGA and build provided examples
* `.github/ <./.github>`_ - Directory with CI configuration and scripts
The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets
with `tuttest <https://github.com/antmicro/tuttest>`_.