fixed image file paths and a few fixes to readmes

Signed-off-by: Joshua Fife <jpfife17@gmail.com>

docs/building-examples.rst

@@ -1,6 +1,6 @@
 
 Building example designs
-========================
+===========================
 
 Before building any example, set the installation directory to match what you
 set it to earlier, for example:
@@ -95,7 +95,7 @@ Enter the directory that contains examples for Xilinx 7-Series FPGAs:
    :file: templates/example.jinja
 
 .. jinja:: xc7_pulse_width_led
-   :file: templates/example.jinja
+   :file: templates/example.jinja 
 
 
 QuickLogic EOS S3

xc7/additional_examples/registers_example/README.rst

@@ -47,3 +47,5 @@ of the register file in action.
    :width: 50%
 
 
+
+

xc7/pulse_width_led/README.rst

@@ -1,5 +1,5 @@
 Pulse Width Modulation
-~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~
 
 This example is built specificity for the arty_35T. It demonstrates a greater variety of I/O and 
 a PWM that drives the RGB leds on the board. To build this example run the following

xc7/timer/README.rst

@@ -26,7 +26,7 @@ Now, you can upload the design with:
 After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
 Press the center button to reset the counter. The following gives a visual example:
 
-.. image:: ../../docs/images/stop-watch.gif
+.. image:: ../../docs/images/timer.gif
    :align: center
    :width: 50%