fixed image file paths and a few fixes to readmes

Signed-off-by: Joshua Fife <jpfife17@gmail.com>
This commit is contained in:
Joshua Fife 2021-07-21 16:41:18 -06:00
parent b03b3292d3
commit 77fc6d315e
9 changed files with 6 additions and 4 deletions

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Building example designs Building example designs
======================== ===========================
Before building any example, set the installation directory to match what you Before building any example, set the installation directory to match what you
set it to earlier, for example: set it to earlier, for example:
@ -95,7 +95,7 @@ Enter the directory that contains examples for Xilinx 7-Series FPGAs:
:file: templates/example.jinja :file: templates/example.jinja
.. jinja:: xc7_pulse_width_led .. jinja:: xc7_pulse_width_led
:file: templates/example.jinja :file: templates/example.jinja
QuickLogic EOS S3 QuickLogic EOS S3

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@ -47,3 +47,5 @@ of the register file in action.
:width: 50% :width: 50%

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Pulse Width Modulation Pulse Width Modulation
~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~
This example is built specificity for the arty_35T. It demonstrates a greater variety of I/O and This example is built specificity for the arty_35T. It demonstrates a greater variety of I/O and
a PWM that drives the RGB leds on the board. To build this example run the following a PWM that drives the RGB leds on the board. To build this example run the following

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@ -26,7 +26,7 @@ Now, you can upload the design with:
After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board. After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
Press the center button to reset the counter. The following gives a visual example: Press the center button to reset the counter. The following gives a visual example:
.. image:: ../../docs/images/stop-watch.gif .. image:: ../../docs/images/timer.gif
:align: center :align: center
:width: 50% :width: 50%