Merge pull request #217 from antmicro/add-litesata

xc7: add lite SATA example

.github/scripts/build-examples.sh

@@ -47,7 +47,7 @@ shift
 
 examples="$@"
 if [ "$fpga_family" == "xc7" -a -z "$examples" ]; then
-    examples="counter picosoc litex litex_linux button_controller timer pulse_width_led hello-a"
+    examples="counter picosoc litex litex_linux litex_sata button_controller timer pulse_width_led hello-a"
 elif [ "$fpga_family" == "eos-s3" -a -z "$examples" ]; then
     examples="counter"
 fi
@@ -74,6 +74,9 @@ if [ "$fpga_family" = "xc7" ]; then
             "litex_linux")
                 snippets="${snippets} xc7/linux_litex_demo/README.rst:example-litex-*-group"
                 ;;
+            "litex_sata")
+                snippets="${snippets} xc7/litex_sata_demo/README.rst:example-litex-sata-*-group"
+                ;;
 
             #Additional examples:
             "button_controller")

.github/scripts/generate_job_matrix.py

@@ -5,6 +5,7 @@ examples = [
     "picosoc",
     "litex",
     "litex_linux",
+    "litex_sata",
     "button_controller",
     "pulse_width_led",
     "timer",

.github/workflows/sphinx-tuttest.yml

@@ -35,7 +35,7 @@ jobs:
     env:
       LANG: "en_US.UTF-8"
       DEBIAN_FRONTEND: "noninteractive"
-      GHA_PREEMPTIBLE: "false" 
+      GHA_PREEMPTIBLE: "false"
 
     container: ${{matrix.os}}:${{matrix.os-version}}
 

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "third_party/projf-explore"]
 	path = third_party/projf-explore
 	url = https://github.com/projf/projf-explore.git
+[submodule "third_party/vexriscv-verilog"]
+	path = third_party/vexriscv-verilog
+	url = https://github.com/m-labs/VexRiscv-verilog

third_party/vexriscv-verilog

@@ -0,0 +1 @@
+Subproject commit 2e4f43d72404a986c9d7251d9d543cf7aef077bc

xc7/linux_litex_demo/Makefile

@@ -1,10 +1,10 @@
 current_dir := ${CURDIR}
 TOP := top
 SOURCES := ${current_dir}/baselitex_arty.v \
-           ${current_dir}/VexRiscv_Linux.v
+           ${current_dir}/../../third_party/vexriscv-verilog/VexRiscv_Linux.v
 
 PCF := ${current_dir}/arty.pcf
 SDC := ${current_dir}/arty.sdc
 XDC := ${current_dir}/arty.xdc
 
-include ${current_dir}/../../common/common.mk 
+include ${current_dir}/../../common/common.mk

xc7/litex_sata_demo/Makefile

@@ -0,0 +1,8 @@
+current_dir := ${CURDIR}
+TOP := top
+SOURCES := ${current_dir}/litesata.v \
+           ${current_dir}/../../third_party/vexriscv-verilog/VexRiscv.v
+
+XDC := ${current_dir}/nexys_video.xdc
+
+include ${current_dir}/../../common/common.mk

xc7/litex_sata_demo/README.rst

@@ -0,0 +1,38 @@
+LiteX SATA demo
+~~~~~~~~~~~~~~~
+
+This example design features a Litex SoC based around VexRiscv soft
+CPU. It also includes a DDR controller and a SATA core.
+
+The design targets the `Nexys Video <https://digilent.com/reference/programmable-logic/nexys-video/start>`_ board, mounting an Artix-7 200T FPGA,
+and the `FMC adapter board <https://github.com/antmicro/fmc-sata-adapter>`_, mounting an M.2 SSD.
+
+To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:
+
+
+.. code-block:: bash
+   :name: example-litex-sata-nexys-video-group
+
+   TARGET="nexys_video" make -C litex_sata_demo
+
+At completion, the bitstreams are located in the build directory:
+
+.. code-block:: bash
+
+   litex_sata_demo/build/<board>
+
+To generate the source files for this test, the following packages were used:
+
+===========================================================  ========================================
+Repo URL                                                     SHA
+===========================================================  ========================================
+`LiteX <https://github.com/enjoy-digital/litex>`_            95b310ee0f0d9e78e00eb32b71324b25265da4f4
+`LiteSATA <https://github.com/enjoy-digital/litesata>`_      fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7
+`LiteDRAM <https://github.com/enjoy-digital/litedram>`_      2c60861929a317af697267d6219da43d10dcf1fa
+`LiteICLink <https://github.com/enjoy-digital/liteiclink>`_  0980a7cf4ffcb0b69a84fa0343a66180408b2a91
+`LiteX Boards <https://github.com/litex-hub/litex-boards>`_  ea58ef94a784308ae024a1d201d603bc8459a590
+`migen <https://github.com/m-labs/migen>`_                   c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5
+===========================================================  ========================================
+
+The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow.
+The fixes are around the GTP high speed transceivers hard blocks.

xc7/litex_sata_demo/mem_2.init

@@ -0,0 +1,45 @@
+4c
+69
+74
+65
+58
+20
+53
+6f
+43
+20
+6f
+6e
+20
+4e
+65
+78
+79
+73
+20
+56
+69
+64
+65
+6f
+20
+32
+30
+32
+31
+2d
+31
+31
+2d
+32
+32
+20
+31
+30
+3a
+31
+32
+3a
+31
+37
+0

xc7/litex_sata_demo/nexys_video.xdc

@@ -0,0 +1,340 @@
+################################################################################
+# IO constraints
+################################################################################
+# serial:0.tx
+set_property LOC AA19 [get_ports {serial_tx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}]
+
+# serial:0.rx
+set_property LOC V18 [get_ports {serial_rx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}]
+
+# cpu_reset:0
+set_property LOC G4 [get_ports {cpu_reset}]
+set_property IOSTANDARD LVCMOS15 [get_ports {cpu_reset}]
+
+# clk100:0
+set_property LOC R4 [get_ports {clk100}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk100}]
+
+# ddram:0.a
+set_property LOC M2 [get_ports {ddram_a[0]}]
+set_property SLEW FAST [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
+
+# ddram:0.a
+set_property LOC M5 [get_ports {ddram_a[1]}]
+set_property SLEW FAST [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
+
+# ddram:0.a
+set_property LOC M3 [get_ports {ddram_a[2]}]
+set_property SLEW FAST [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
+
+# ddram:0.a
+set_property LOC M1 [get_ports {ddram_a[3]}]
+set_property SLEW FAST [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
+
+# ddram:0.a
+set_property LOC L6 [get_ports {ddram_a[4]}]
+set_property SLEW FAST [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
+
+# ddram:0.a
+set_property LOC P1 [get_ports {ddram_a[5]}]
+set_property SLEW FAST [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
+
+# ddram:0.a
+set_property LOC N3 [get_ports {ddram_a[6]}]
+set_property SLEW FAST [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
+
+# ddram:0.a
+set_property LOC N2 [get_ports {ddram_a[7]}]
+set_property SLEW FAST [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
+
+# ddram:0.a
+set_property LOC M6 [get_ports {ddram_a[8]}]
+set_property SLEW FAST [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
+
+# ddram:0.a
+set_property LOC R1 [get_ports {ddram_a[9]}]
+set_property SLEW FAST [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
+
+# ddram:0.a
+set_property LOC L5 [get_ports {ddram_a[10]}]
+set_property SLEW FAST [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
+
+# ddram:0.a
+set_property LOC N5 [get_ports {ddram_a[11]}]
+set_property SLEW FAST [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
+
+# ddram:0.a
+set_property LOC N4 [get_ports {ddram_a[12]}]
+set_property SLEW FAST [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
+
+# ddram:0.a
+set_property LOC P2 [get_ports {ddram_a[13]}]
+set_property SLEW FAST [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
+
+# ddram:0.a
+set_property LOC P6 [get_ports {ddram_a[14]}]
+set_property SLEW FAST [get_ports {ddram_a[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
+
+# ddram:0.ba
+set_property LOC L3 [get_ports {ddram_ba[0]}]
+set_property SLEW FAST [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
+
+# ddram:0.ba
+set_property LOC K6 [get_ports {ddram_ba[1]}]
+set_property SLEW FAST [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
+
+# ddram:0.ba
+set_property LOC L4 [get_ports {ddram_ba[2]}]
+set_property SLEW FAST [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
+
+# ddram:0.ras_n
+set_property LOC J4 [get_ports {ddram_ras_n}]
+set_property SLEW FAST [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
+
+# ddram:0.cas_n
+set_property LOC K3 [get_ports {ddram_cas_n}]
+set_property SLEW FAST [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
+
+# ddram:0.we_n
+set_property LOC L1 [get_ports {ddram_we_n}]
+set_property SLEW FAST [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
+
+# ddram:0.dm
+set_property LOC G3 [get_ports {ddram_dm[0]}]
+set_property SLEW FAST [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
+
+# ddram:0.dm
+set_property LOC F1 [get_ports {ddram_dm[1]}]
+set_property SLEW FAST [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
+
+# ddram:0.dq
+set_property LOC G2 [get_ports {ddram_dq[0]}]
+set_property SLEW FAST [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
+
+# ddram:0.dq
+set_property LOC H4 [get_ports {ddram_dq[1]}]
+set_property SLEW FAST [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
+
+# ddram:0.dq
+set_property LOC H5 [get_ports {ddram_dq[2]}]
+set_property SLEW FAST [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
+
+# ddram:0.dq
+set_property LOC J1 [get_ports {ddram_dq[3]}]
+set_property SLEW FAST [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
+
+# ddram:0.dq
+set_property LOC K1 [get_ports {ddram_dq[4]}]
+set_property SLEW FAST [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
+
+# ddram:0.dq
+set_property LOC H3 [get_ports {ddram_dq[5]}]
+set_property SLEW FAST [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
+
+# ddram:0.dq
+set_property LOC H2 [get_ports {ddram_dq[6]}]
+set_property SLEW FAST [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
+
+# ddram:0.dq
+set_property LOC J5 [get_ports {ddram_dq[7]}]
+set_property SLEW FAST [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
+
+# ddram:0.dq
+set_property LOC E3 [get_ports {ddram_dq[8]}]
+set_property SLEW FAST [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
+
+# ddram:0.dq
+set_property LOC B2 [get_ports {ddram_dq[9]}]
+set_property SLEW FAST [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
+
+# ddram:0.dq
+set_property LOC F3 [get_ports {ddram_dq[10]}]
+set_property SLEW FAST [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
+
+# ddram:0.dq
+set_property LOC D2 [get_ports {ddram_dq[11]}]
+set_property SLEW FAST [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
+
+# ddram:0.dq
+set_property LOC C2 [get_ports {ddram_dq[12]}]
+set_property SLEW FAST [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
+
+# ddram:0.dq
+set_property LOC A1 [get_ports {ddram_dq[13]}]
+set_property SLEW FAST [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
+
+# ddram:0.dq
+set_property LOC E2 [get_ports {ddram_dq[14]}]
+set_property SLEW FAST [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
+
+# ddram:0.dq
+set_property LOC B1 [get_ports {ddram_dq[15]}]
+set_property SLEW FAST [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
+
+# ddram:0.dqs_p
+set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
+
+# ddram:0.dqs_p
+set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
+
+# ddram:0.dqs_n
+set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
+
+# ddram:0.dqs_n
+set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
+
+# ddram:0.clk_p
+set_property LOC P5 [get_ports {ddram_clk_p}]
+set_property SLEW FAST [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
+
+# ddram:0.clk_n
+set_property LOC P4 [get_ports {ddram_clk_n}]
+set_property SLEW FAST [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
+
+# ddram:0.cke
+set_property LOC J6 [get_ports {ddram_cke}]
+set_property SLEW FAST [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
+
+# ddram:0.odt
+set_property LOC K4 [get_ports {ddram_odt}]
+set_property SLEW FAST [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
+
+# ddram:0.reset_n
+set_property LOC G1 [get_ports {ddram_reset_n}]
+set_property SLEW FAST [get_ports {ddram_reset_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
+
+# fmc2sata:0.clk_p
+set_property LOC F10 [get_ports {fmc2sata_clk_p}]
+
+# fmc2sata:0.clk_n
+set_property LOC E10 [get_ports {fmc2sata_clk_n}]
+
+# fmc2sata:0.tx_p
+set_property LOC D7 [get_ports {fmc2sata_tx_p}]
+
+# fmc2sata:0.tx_n
+set_property LOC C7 [get_ports {fmc2sata_tx_n}]
+
+# fmc2sata:0.rx_p
+set_property LOC D9 [get_ports {fmc2sata_rx_p}]
+
+# fmc2sata:0.rx_n
+set_property LOC C9 [get_ports {fmc2sata_rx_n}]
+
+# user_led:0
+set_property LOC T14 [get_ports {user_led0}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led0}]
+
+# user_led:1
+set_property LOC T15 [get_ports {user_led1}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led1}]
+
+# user_led:2
+set_property LOC T16 [get_ports {user_led2}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led2}]
+
+# user_led:3
+set_property LOC U16 [get_ports {user_led3}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led3}]
+
+# user_led:4
+set_property LOC V15 [get_ports {user_led4}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led4}]
+
+# user_led:5
+set_property LOC W16 [get_ports {user_led5}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led5}]
+
+# user_led:6
+set_property LOC W15 [get_ports {user_led6}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led6}]
+
+# user_led:7
+set_property LOC Y13 [get_ports {user_led7}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led7}]
+
+# vadj:0
+set_property LOC AA13 [get_ports {vadj[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {vadj[0]}]
+
+# vadj:1
+set_property LOC AB17 [get_ports {vadj[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {vadj[1]}]
+
+################################################################################
+# Design constraints
+################################################################################
+
+set_property INTERNAL_VREF 0.750 [get_iobanks 35]
+
+################################################################################