added nexys_video files and docs for picosoc_demo
Signed-off-by: Ezra Thomas <ept@seas.upenn.edu>
This commit is contained in:
parent
e3a23897c2
commit
7b7d9e0058
|
@ -16,6 +16,9 @@ else ifeq ($(TARGET),arty_100)
|
|||
else ifeq ($(TARGET),nexys4ddr)
|
||||
SOURCES += ${current_dir}/nexys4ddr.v
|
||||
PCF := ${current_dir}/nexys4ddr.pcf
|
||||
else ifeq ($(TARGET),nexys_video)
|
||||
SOURCES += ${current_dir}/nexysvideo.v
|
||||
PCF := ${current_dir}/nexysvideo.pcf
|
||||
else
|
||||
SOURCES += ${current_dir}/basys3.v
|
||||
PCF := ${current_dir}/basys3.pcf
|
||||
|
|
|
@ -26,6 +26,11 @@ This example features a picorv32 soft CPU and a SoC based on it. To build the pi
|
|||
|
||||
TARGET="basys3" make -C picosoc_demo
|
||||
|
||||
.. code-block:: bash
|
||||
:name: example-picosoc-nexys_video-group
|
||||
|
||||
TARGET="nexys_video" make -C picosoc_demo
|
||||
|
||||
At completion, the bitstreams are located in the build directory:
|
||||
|
||||
.. code-block:: bash
|
||||
|
|
|
@ -0,0 +1,26 @@
|
|||
# 100 MHz CLK
|
||||
set_io clk R4
|
||||
|
||||
# UART
|
||||
set_io rx V18
|
||||
set_io tx AA19
|
||||
|
||||
# LEDs
|
||||
set_io led[0] T14
|
||||
set_io led[1] T15
|
||||
set_io led[2] T16
|
||||
set_io led[3] U16
|
||||
set_io led[4] V15
|
||||
set_io led[5] W16
|
||||
set_io led[6] W15
|
||||
set_io led[7] Y13
|
||||
|
||||
# SWs
|
||||
set_io sw[0] E22
|
||||
set_io sw[1] F21
|
||||
set_io sw[2] G21
|
||||
set_io sw[3] G22
|
||||
set_io sw[4] H17
|
||||
set_io sw[5] J16
|
||||
set_io sw[6] K13
|
||||
set_io sw[7] M17
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* PicoSoC - A simple example SoC using PicoRV32
|
||||
*
|
||||
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
|
||||
output tx,
|
||||
input rx,
|
||||
|
||||
input [7:0] sw,
|
||||
output [7:0] led,
|
||||
);
|
||||
|
||||
wire clk_bufg;
|
||||
BUFG bufg (.I(clk), .O(clk_bufg));
|
||||
|
||||
reg [5:0] reset_cnt = 0;
|
||||
wire resetn = &reset_cnt;
|
||||
|
||||
always @(posedge clk_bufg) begin
|
||||
reset_cnt <= reset_cnt + !resetn;
|
||||
end
|
||||
|
||||
wire iomem_valid;
|
||||
reg iomem_ready;
|
||||
wire [3:0] iomem_wstrb;
|
||||
wire [31:0] iomem_addr;
|
||||
wire [31:0] iomem_wdata;
|
||||
reg [31:0] iomem_rdata;
|
||||
|
||||
reg [31:0] gpio;
|
||||
|
||||
assign led = gpio[7:0];
|
||||
|
||||
always @(posedge clk_bufg) begin
|
||||
if (!resetn) begin
|
||||
gpio <= 0;
|
||||
end else begin
|
||||
iomem_ready <= 0;
|
||||
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
|
||||
iomem_ready <= 1;
|
||||
iomem_rdata <= {2{sw, gpio[7:0]}};
|
||||
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
|
||||
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
|
||||
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
|
||||
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
picosoc_noflash soc (
|
||||
.clk(clk_bufg),
|
||||
.resetn(resetn),
|
||||
|
||||
.ser_tx(tx),
|
||||
.ser_rx(rx),
|
||||
|
||||
.irq_5(1'b0),
|
||||
.irq_6(1'b0),
|
||||
.irq_7(1'b0),
|
||||
|
||||
.iomem_valid(iomem_valid),
|
||||
.iomem_ready(iomem_ready),
|
||||
.iomem_wstrb(iomem_wstrb),
|
||||
.iomem_addr(iomem_addr),
|
||||
.iomem_wdata(iomem_wdata),
|
||||
.iomem_rdata(iomem_rdata)
|
||||
);
|
||||
|
||||
endmodule
|
Loading…
Reference in New Issue