Add QuickLogic EOS-S3 example

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

README.md

@@ -1,7 +1,7 @@
 # SymbiFlow examples
 
 This repository provides example FPGA designs that can be built using the SymbiFlow open source toolchain.
-The examples target the Xilinx Artix-7 devices.
+The examples target the Xilinx Artix-7 and the QuickLogic EOS S3 devices.
 
 The repository includes:
 
@@ -46,16 +46,36 @@ pip install git+https://github.com/symbiflow/fasm
 conda deactivate
 ```
 
+For the EOS S3 devices:
+
+```bash
+INSTALL_DIR="/opt/symbiflow/eos-s3"
+bash conda_installer.sh -b -p $INSTALL_DIR/conda && rm conda_installer.sh
+source "$INSTALL_DIR/conda/etc/profile.d/conda.sh"
+conda update -y -q conda
+
+wget -qO- https://storage.googleapis.com/symbiflow-arch-defs-install/quicklogic/arch-defs-install-eos-s3-f7880e1f.tar.xz | tar -xJ -C $INSTALL_DIR
+conda install -y -c antmicro/label/ql yosys yosys-plugins vtr-no-gui
+conda install -y make lxml simplejson intervaltree git pip
+conda activate
+pip install python-constraint
+pip install git+https://github.com/symbiflow/fasm
+pip install git+https://github.com/antmicro/quicklogic-fasm
+pip install git+https://github.com/antmicro/quicklogic-fasm-utils
+conda deactivate
+```
+
 ## Build Example Designs
 
 With the toolchain installed, you can build the example designs.
 The example designs are provided in separate directories:
 
 * `examples/xc7` directory for the Artix-7 devices
+* `examples/eos-s3` directory for the EOS S3 devices
 
 ### Example designs for the Artix-7 devices:
 
-1. `counter` - simple 4-bit counter driving LEDs. The design targets the [Basys3 board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/)
+1. `counter` - simple 4-bit counter driving LEDs. The design targets the [Basys3 board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/) and the [Arty board](https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/).
 1. `picosoc` - [picorv32](https://github.com/cliffordwolf/picorv32) based SoC. The design targets the [Basys3 board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/).
 1. `linux_litex` - [LiteX](https://github.com/enjoy-digital/litex) based system with Linux capable [VexRiscv core](https://github.com/SpinalHDL/VexRiscv). The design includes [DDR](https://github.com/enjoy-digital/litedram) and [Ethernet](https://github.com/enjoy-digital/liteeth) controllers. The design targets the [Arty board](https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/).
 
@@ -78,3 +98,19 @@ pushd examples/xc7/picosoc_demo && make && popd
 # litex example
 pushd examples/xc7/linux_litex_demo && make && popd
 ```
+
+### Example design for the EOS S3 devices:
+
+1. `btn_counter` - simple 4-bit counter driving LEDs. The design targets the [EOS S3 FPGA](https://www.quicklogic.com/products/eos-s3/).
+
+To build the example, run the following commands:
+
+```bash
+export INSTALL_DIR="/opt/symbiflow/eos-s3"
+# adding symbiflow toolchain binaries to PATH
+export PATH="$INSTALL_DIR/install/bin:$PATH"
+source "$INSTALL_DIR/conda/etc/profile.d/conda.sh"
+conda activate
+git clone https://github.com/SymbiFlow/symbiflow-examples && cd symbiflow-examples
+pushd examples/eos-s3 && make && popd
+```

examples/eos-s3/Makefile

@@ -0,0 +1,36 @@
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
+TOP:=top
+VERILOG:=${current_dir}/btn_counter.v
+PARTNAME:= ql-eos-s3_wlcsp
+DEVICE  := ql-eos-s3_wlcsp
+BITSTREAM_DEVICE := ql-eos-s3_wlcsp
+PCF:=${current_dir}/chandalar.pcf
+BUILDDIR:=build
+
+all: ${BUILDDIR}/${TOP}.bit
+
+${BUILDDIR}:
+	mkdir ${BUILDDIR}
+
+${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
+	cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -P ${PCF}
+
+${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
+	cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
+	cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME}
+
+${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
+	cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
+	cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}
+
+${BUILDDIR}/${TOP}.bit: ${BUILDDIR}/${TOP}.fasm
+	cd ${BUILDDIR} && write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
+
+clean:
+	rm -rf ${BUILDDIR}
+

examples/eos-s3/btn_counter.v

@@ -0,0 +1,14 @@
+module top(
+    input  wire       clk,
+    output wire [3:0] led
+);
+
+    reg [3:0] cnt;
+    initial cnt <= 0;
+
+    always @(posedge clk)
+        cnt <= cnt + 1;
+
+    assign led = cnt;
+
+endmodule

examples/eos-s3/chandalar.pcf

@@ -0,0 +1,5 @@
+set_io clk      FBIO_0
+set_io led(0)   FBIO_21
+set_io led(1)   FBIO_22
+set_io led(2)   FBIO_26
+set_io led(3)   FBIO_18

examples/eos-s3/quickfeather.pcf

@@ -0,0 +1,5 @@
+set_io clk      FBIO_6
+set_io led(0)   FBIO_22
+set_io led(1)   FBIO_21
+set_io led(2)   FBIO_18
+set_io led(3)   FBIO_30