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f4pga-examples
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formatted files 

Signed-off-by: Ryan Johnson <ryancj14@gmail.com>
This commit is contained in:
Ryan Johnson 2021-05-13 12:05:33 -06:00
parent 1baae70b14
commit 9b953d9f75
12 changed files with 16555 additions and 16195 deletions
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18
docs/collect_readmes.py
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@ -1,7 +1,6 @@
import os
from docutils.core import publish_doctree
full_name_lut = {
'a35t': 'Arty 35T',
'a100t': 'Arty 100T',
@ -29,10 +28,11 @@ def handle_default_with_inlines(block):
"""
text = ""
for node in block.traverse(include_self=False, condition=lambda x:
x.parent.tagname.strip() not in inlines):
for node in block.traverse(
include_self=False,
condition=lambda x: x.parent.tagname.strip() not in inlines):
tagname = node.tagname.strip()
if tagname in ('paragraph',):
if tagname in ('paragraph', ):
continue
if tagname == 'literal':
@ -149,8 +149,8 @@ def handle_note(block):
ret['type'] = block.tagname.strip()
if sum(map(lambda x: subtree_has_tag(block, x), inlines)):
for node in block.traverse(condition=lambda x:
x.tagname.strip() == 'paragraph'):
for node in block.traverse(
condition=lambda x: x.tagname.strip() == 'paragraph'):
ret['text'] = handle_default_with_inlines(node)['text']
else:
ret['text'] = block.astext()
@ -204,8 +204,10 @@ def get_blocks(text):
"""
doctree = publish_doctree(text)
return doctree.traverse(condition=lambda x: x.tagname.strip() != 'document'
and x.parent.tagname.strip() != 'note')
return doctree.traverse(
condition=lambda x: x.tagname.strip() != 'document' and x.parent.
tagname.strip() != 'note'
)
def fill_context(text):

11
eos-s3/btn_counter/btn_counter.v
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@ -1,14 +1,13 @@
module top(
module top (
input wire clk,
output wire [3:0] led
);
reg [3:0] cnt;
initial cnt <= 0;
reg [3:0] cnt;
initial cnt <= 0;
always @(posedge clk)
cnt <= cnt + 1;
always @(posedge clk) cnt <= cnt + 1;
assign led = cnt;
assign led = cnt;
endmodule

23
xc7/counter_test/counter.v
View File

@ -1,19 +1,22 @@
module top (
input clk,
input clk,
output [3:0] led
);
localparam BITS = 4;
localparam LOG2DELAY = 22;
localparam BITS = 4;
localparam LOG2DELAY = 22;
wire bufg;
BUFG bufgctrl(.I(clk), .O(bufg));
wire bufg;
BUFG bufgctrl (
.I(clk),
.O(bufg)
);
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge bufg) begin
counter <= counter + 1;
end
always @(posedge bufg) begin
counter <= counter + 1;
end
assign led[3:0] = counter >> LOG2DELAY;
assign led[3:0] = counter >> LOG2DELAY;
endmodule

49
xc7/counter_test/counter_zynq.v
View File

@ -1,36 +1,37 @@
module top(
input wire clk,
module top (
input wire clk,
output wire [3:0] led
);
wire [63:0] emio_gpio_o;
wire [63:0] emio_gpio_t;
wire [63:0] emio_gpio_i;
wire [63:0] emio_gpio_o;
wire [63:0] emio_gpio_t;
wire [63:0] emio_gpio_i;
wire clk_bufg;
BUFG BUFG(.I(clk), .O(clk_bufg));
wire clk_bufg;
BUFG BUFG (
.I(clk),
.O(clk_bufg)
);
wire en_counter = ~emio_gpio_o[0];
wire count_direction = ~emio_gpio_o[1];
reg [31:0] counter = 0;
wire en_counter = ~emio_gpio_o[0];
wire count_direction = ~emio_gpio_o[1];
reg [31:0] counter = 0;
always @(posedge clk_bufg) begin
always @(posedge clk_bufg) begin
if (en_counter)
if (count_direction)
counter <= counter + 1;
else
counter <= counter - 1;
end
if (count_direction) counter <= counter + 1;
else counter <= counter - 1;
end
assign led = counter[27:24];
assign led = counter[27:24];
// The PS7
(* KEEP, DONT_TOUCH *)
PS7 PS7(
.EMIOGPIOO (emio_gpio_o),
.EMIOGPIOTN (emio_gpio_t),
.EMIOGPIOI (emio_gpio_i),
);
// The PS7
(* KEEP, DONT_TOUCH *)
PS7 PS7 (
.EMIOGPIOO (emio_gpio_o),
.EMIOGPIOTN(emio_gpio_t),
.EMIOGPIOI (emio_gpio_i),
);
endmodule

1
xc7/linux_litex_demo/VexRiscv_Linux.v
View File

@ -7466,4 +7466,3 @@ module VexRiscv (
end
endmodule

32170
xc7/linux_litex_demo/baselitex_arty.v
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File diff suppressed because one or more lines are too long

8
xc7/linux_litex_demo/images.json
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@ -1,6 +1,6 @@
{
"buildroot/Image": "0xc0000000",
"buildroot/rootfs.cpio": "0xc0800000",
"buildroot/rv32.dtb": "0xc1000000",
"emulator/emulator.bin": "0x50000000"
"buildroot/Image": "0xc0000000",
"buildroot/rootfs.cpio": "0xc0800000",
"buildroot/rv32.dtb": "0xc1000000",
"emulator/emulator.bin": "0x50000000"
}

103
xc7/picosoc_demo/arty.v
View File

@ -18,69 +18,72 @@
*/
module top (
input clk,
input clk,
output tx,
input rx,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (.I(clk), .O(clk_bufg));
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
reg [31:0] gpio;
assign led = gpio[3:0];
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn (resetn ),
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx (tx),
.ser_rx (rx),
.ser_tx(tx),
.ser_rx(rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule

103
xc7/picosoc_demo/basys3.v
View File

@ -18,69 +18,72 @@
*/
module top (
input clk,
input clk,
output tx,
input rx,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
input [15:0] sw,
output [15:0] led
);
wire clk_bufg;
BUFG bufg (.I(clk), .O(clk_bufg));
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
reg [31:0] gpio;
assign led = gpio[15:0];
assign led = gpio[15:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn (resetn ),
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx (tx),
.ser_rx (rx),
.ser_tx(tx),
.ser_rx(rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule

1
xc7/picosoc_demo/picosoc_noflash.v
View File

@ -255,4 +255,3 @@ module picosoc_mem #(
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule

60
xc7/picosoc_demo/progmem.v
View File

@ -1,30 +1,29 @@
module progmem
(
// Closk & reset
input wire clk,
input wire rstn,
module progmem (
// Closk & reset
input wire clk,
input wire rstn,
// PicoRV32 bus interface
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] rdata
// PicoRV32 bus interface
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] rdata
);
// ============================================================================
// ============================================================================
localparam MEM_SIZE_BITS = 10; // In 32-bit words
localparam MEM_SIZE = 1 << MEM_SIZE_BITS;
localparam MEM_ADDR_MASK = 32'h0010_0000;
localparam MEM_SIZE_BITS = 10; // In 32-bit words
localparam MEM_SIZE = 1 << MEM_SIZE_BITS;
localparam MEM_ADDR_MASK = 32'h0010_0000;
// ============================================================================
// ============================================================================
wire [MEM_SIZE_BITS-1:0] mem_addr;
reg [31:0] mem_data;
reg [31:0] mem[0:MEM_SIZE];
wire [MEM_SIZE_BITS-1:0] mem_addr;
reg [ 31:0] mem_data;
reg [ 31:0] mem [0:MEM_SIZE];
initial begin
initial begin
mem['h0000] <= 32'h00000093;
mem['h0001] <= 32'h00000193;
mem['h0002] <= 32'h00000213;
@ -786,22 +785,21 @@ initial begin
mem['h02F6] <= 32'h3E646E61;
mem['h02F7] <= 32'h00000020;
end
end
always @(posedge clk)
mem_data <= mem[mem_addr];
always @(posedge clk) mem_data <= mem[mem_addr];
// ============================================================================
// ============================================================================
reg o_ready;
reg o_ready;
always @(posedge clk or negedge rstn)
if (!rstn) o_ready <= 1'd0;
else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0);
always @(posedge clk or negedge rstn)
if (!rstn) o_ready <= 1'd0;
else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0);
// Output connectins
assign ready = o_ready;
assign rdata = mem_data;
assign mem_addr = addr[MEM_SIZE_BITS+1:2];
// Output connectins
assign ready = o_ready;
assign rdata = mem_data;
assign mem_addr = addr[MEM_SIZE_BITS+1:2];
endmodule

203
xc7/picosoc_demo/simpleuart.v
View File

@ -18,120 +18,115 @@
*/
module simpleuart (
input clk,
input resetn,
input clk,
input resetn,
output ser_tx,
input ser_rx,
output ser_tx,
input ser_rx,
input [3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input [ 3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
);
reg [31:0] cfg_divider;
reg [31:0] cfg_divider;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
assign reg_div_do = cfg_divider;
assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[7:0] <= reg_div_di[7:0];
if (reg_div_we[1]) cfg_divider[15:8] <= reg_div_di[15:8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re)
recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx)
recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2*recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re) recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx) recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2 * recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
assign ser_tx = send_pattern[0];
assign ser_tx = send_pattern[0];
always @(posedge clk) begin
if (reg_div_we)
send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else
if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else
if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
always @(posedge clk) begin
if (reg_div_we) send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
endmodule