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f4pga-examples
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Change arty_50 to arty_35 to match board branding. 

Signed-off-by: Tim Callahan <tcal@google.com>
This commit is contained in:
Tim Callahan 2020-10-13 16:21:28 -07:00
parent eeabde6659
commit cdfac6ca4e
3 changed files with 5 additions and 5 deletions
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2
README.rst
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@ -139,7 +139,7 @@ To build the counter example, run any or all of the following commands:
.. code:: bash
:name: xc7-counter
pushd xc7/counter_test && make clean && TARGET="arty_50" make && popd
pushd xc7/counter_test && make clean && TARGET="arty_35" make && popd
pushd xc7/counter_test && make clean && TARGET="arty_100" make && popd
pushd xc7/counter_test && make clean && TARGET="basys3" make && popd

6
xc7/README.rst
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@ -1,11 +1,11 @@
SymbiFlow Toolchain Examples for Xilinx 7 Series
================================================
#. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__ and the `Arty board <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
#. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__ and the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
#. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
#. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty board <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
#. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
The Linux images for the ``linux_litex`` example can be built following the `linux on litex vexriscv <https://github.com/litex-hub/linux-on-litex-vexriscv>`__ instructions.
The ``linux_litex`` example is already provided with working Linux images.
@ -72,7 +72,7 @@ To build the counter example, run any or all of the following commands:
.. code:: bash
:name: xc7-counter
pushd xc7/counter_test && make clean && TARGET="arty_50" make && popd
pushd xc7/counter_test && make clean && TARGET="arty_35" make && popd
pushd xc7/counter_test && make clean && TARGET="arty_100" make && popd
pushd xc7/counter_test && make clean && TARGET="basys3" make && popd

2
xc7/counter_test/Makefile
View File

@ -7,7 +7,7 @@ BITSTREAM_DEVICE := artix7
SDC:=${current_dir}/counter.sdc
BUILDDIR:=build
ifeq ($(TARGET),arty_50)
ifeq ($(TARGET),arty_35)
PARTNAME := xc7a35tcsg324-1
PCF:=${current_dir}/arty.pcf
else ifeq ($(TARGET),arty_100)