Add counter demo for Arty

Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
This commit is contained in:
Joanna Brozek 2020-06-10 10:03:21 +02:00
parent 8338e1df18
commit ce1c9cc9c5
5 changed files with 22 additions and 37 deletions

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@ -2,13 +2,19 @@ mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP:=top
VERILOG:=${current_dir}/counter.v
PARTNAME:= xc7a35tcpg236-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF:=${current_dir}/basys3.pcf
SDC:=${current_dir}/basys3.sdc
SDC:=${current_dir}/counter.sdc
BUILDDIR:=build
ifeq ($(TARGET),arty)
PARTNAME := xc7a35tcsg324-1
PCF:=${current_dir}/arty.pcf
else
PARTNAME:= xc7a35tcpg236-1
PCF:=${current_dir}/basys3.pcf
endif
all: ${BUILDDIR}/${TOP}.bit
${BUILDDIR}:

12
examples/xc7/counter_test/arty.pcf vendored Normal file
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@ -0,0 +1,12 @@
# 100 MHz CLK
set_io clk E3
# UART
set_io rx A9
set_io tx D10
# LEDs
set_io led[0] H5
set_io led[1] J5
set_io led[2] T9
set_io led[3] T10

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@ -3,39 +3,9 @@ set_io clk W5
set_io tx A18
set_io rx B18
#
# in[0:15] correspond with SW0-SW15 on the basys3
set_io sw[0] V17
set_io sw[1] V16
set_io sw[2] W16
set_io sw[3] W17
set_io sw[4] W15
set_io sw[5] V15
set_io sw[6] W14
set_io sw[7] W13
set_io sw[8] V2
set_io sw[9] T3
set_io sw[10] T2
set_io sw[11] R3
set_io sw[12] W2
set_io sw[13] U1
set_io sw[14] T1
set_io sw[15] R2
# out[0:15] correspond with LD0-LD15 on the basys3
set_io led[0] U16
set_io led[1] E19
set_io led[2] U19
set_io led[3] V19
set_io led[4] W18
set_io led[5] U15
set_io led[6] U14
set_io led[7] V14
set_io led[8] V13
set_io led[9] V3
set_io led[10] W3
set_io led[11] U3
set_io led[12] P3
set_io led[13] N3
set_io led[14] P1
set_io led[15] L1

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@ -2,8 +2,7 @@ module top (
input clk,
input rx,
output tx,
input [15:0] sw,
output [15:0] led
output [3:0] led
);
localparam BITS = 4;
@ -19,7 +18,5 @@ module top (
end
assign led[3:0] = counter >> LOG2DELAY;
assign led[14:4] = sw[14:4];
assign tx = rx;
assign led[15] = ^sw;
endmodule