Merge pull request #178 from WhiteNinjaZ/doc-update
Makefile Doc update
This commit is contained in:
commit
fc396d88cc
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@ -2,121 +2,73 @@ Customizing the Makefiles
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==========================
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A powerful tool in creating your own designs is understanding how to generate your own Makefile to
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compile projects. This tutorial walks you through some of the key aspects of working with Makefiles
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and explains how you can create Makefiles for your own designs.
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compile projects. This tutorial walks you through how to do that.
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If you would like to use methods other than a Makefile to build and compile your designs
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(such as python or bash scripts) or if you would like to learn more about the various Symbiflow
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commands used by the Makefile to build and compile designs take a look at the
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commands used by the common Makefile to build and compile designs take a look at the
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`Understanding Toolchain Commands <understanding-commands.html>`_ page.
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Example
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-------
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Every example design in Symbiflow has its own Makefile. For example
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`counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_,
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`Linux Litex demo <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/linux_litex_demo/Makefile>`_,
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and `PicoSoC demo <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/picosoc_demo/Makefile>`_
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all have there own unique Makefiles for compiling and building respective designs. To understand
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how to set up a Makefile in Symbiflow, lets take a look at a simple Makefile. The following code
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is based on the Makefile within `counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_
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and has been modified slightly for simplicity. Highlighted lines within the code below are of
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particular interest and will change depending on your specific design elements and hardware.
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Lines that are not highlighted do not change from design to design and can be copy and pasted
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into your own Makefile.
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By including Symbiflow's provided common Makefile in your designs, running the commands necessary for building
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your personal projects is incredibly simple. All you have to do is run a few simple commands and set
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a few variables.
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Create a makefile for your project by running ``touch Makefile``, and add the following to the contents.
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.. code-block:: bash
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:name: makefile-example
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:emphasize-lines: 3, 4, 5, 6, 9, 10, 22, 25, 28, 31
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:linenos:
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
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TOP := top
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VERILOG := ${current_dir}/counter.v
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DEVICE := xc7a50t_test
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BITSTREAM_DEVICE := artix7
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BUILDDIR := build
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current_dir := ${CURDIR}
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TOP := <put the name of your top module here>
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SOURCES := ${current_dir}/<put your HDL sources here>
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# Include your constraint file path(s) below. Use either an XDC file
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# or a PCF+SDC pair. Don't use all three file types.
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XDC := ${current_dir}/<name of your pcf file if applicable>
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PCF := ${current_dir}/<name of your xdc file if applicable>
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SDC := ${current_dir}/<name of your sdc file if applicable>
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PARTNAME := xc7a35tcpg236-1
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XDC := ${current_dir}/basys3.xdc
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BOARD_BUILDDIR := ${BUILDDIR}/basys3
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include <path to symbiflow-examples root directory>/common/common.mk
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Lets talk briefly about each of the commands in the above makefile
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.DELETE_ON_ERROR:
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Adding HDL Sources and Specifying the Top Module
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------------------------------------------------
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all: ${BOARD_BUILDDIR}/${TOP}.bit
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:ref:`Line 2<makefile-example>` in the Makefile shows how to define the name for your top level module.
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For example, if your top module was named ``module switches ( ...`` then you would simply uncomment
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line 3 and change the text in ``<>`` to ``TOP := switches``.
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${BOARD_BUILDDIR}:
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mkdir -p ${BOARD_BUILDDIR}
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
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cd ${BOARD_BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}
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${BOARD_BUILDDIR}/${TOP}.bit: ${BOARD_BUILDDIR}/${TOP}.fasm
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cd ${BOARD_BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
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clean:
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rm -rf ${BUILDDIR}
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Adding HDL files to your design
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--------------------------------
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:ref:`Line 3 <makefile-example>` in the Makefile shows how to define the name for your top level module. For example, if
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your top module was named ``module switches ( ...`` then you would simply change line 3 to
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``TOP := switches``.
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.. warning::
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If you change the name of your top level module then the command you use to download the bitstream to
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your board using ``openocd`` will need to change slightly from what is provided in the examples. For
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instance, if you changed the top level module name to ``TOP := my_module_top`` then the openocd command
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would change to:
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.. code-block:: bash
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openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 my_module_top.bit; exit"
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Note that the only part of the command that changes is "<top module name>.bit;"
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:ref:`Line 4 <makefile-example>` in the Makefile shows how to add HDL files to the design. The general syntax is:
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``<HDL language>:=${current_dir}/<your HDL file path>``. You can also add multiple HDL files to a
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:ref:`Line 3<makefile-example>` in the Makefile shows how to add HDL files to the design. The general
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syntax is: ``SOURCES:=${current_dir}/<your HDL file path>``. You can also add multiple HDL files to a
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design using the following syntax:
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.. code-block:: bash
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:name: multi-file-example
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<HDL language> := ${current_dir}/<HDL file 1> \
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${current_dir}/<HDL file 2> \
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${current_dir}/<HDL file 3> \
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${current_dir}/<HDL file 4> \
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...
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SOURCES := ${current_dir}/<HDL file 1> \
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${current_dir}/<HDL file 2> \
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${current_dir}/<HDL file 3> \
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...
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${current_dir}/<HDL file n> \
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You could also use wildcards to collect all HDL file types of a specific extension and add them
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to your design. For example, if you wanted to add all verilog files within the current directory
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to your design, you could replace line 4 in the Makefile with:
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to your design, you could replace line 3 in the Makefile with:
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.. code-block:: bash
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:name: wildcard-example
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VERILOG := ${current_dir}/*.v
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SOURCES := ${current_dir}/*.v
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To include SystemVerilog HDL in your designs simply change the ``.v`` extension in the examples
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above to a ``.sv``. You might also want to change the ``VERILOG`` bash variables throughout the
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Makefile to ``SYSTEM_VERILOG`` to improve readability.
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above to a ``.sv``.
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.. note::
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@ -124,114 +76,12 @@ Makefile to ``SYSTEM_VERILOG`` to improve readability.
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SystemVerilog can also be run through the toolchain but more complicated
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designs may not be fully supported.
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Setting the Board Type and Part Name
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-------------------------------------
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:ref:`Line 5 <makefile-example>` in the example Makefile defines the device fabric
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for the board being used in the project. Several different device fabrics are
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supported and a listing of the commands for each follow:
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.. tabs::
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.. group-tab:: Arty_35T
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.. code-block:: bash
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:name: example-counter-a35t-group
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DEVICE := xc7a50t_test
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.. group-tab:: Arty_100T
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.. code-block:: bash
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:name: example-counter-a100t-group
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DEVICE := xc7a100t_test
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.. group-tab:: Nexus 4 DDR
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.. code-block:: bash
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:name: example-counter-nexys4ddr-group
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DEVICE := xc7a100t_test
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.. group-tab:: Basys3
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.. code-block:: bash
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:name: example-counter-basys3-group
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DEVICE := xc7a50t_test
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.. group-tab:: Zybo Z7
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.. code-block:: bash
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:name: example-counter-zybo-group
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DEVICE := xc7z010_test
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.. group-tab:: Nexys Video
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.. code-block:: bash
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:name: example-counter-nexys_video-group
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DEVICE := xc7a200t_test
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:ref:`Line 7 <makefile-example>` defines the family for your FPGA. For example basys3 and arty boards are from the artix7
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family while zybo boards are from the zynq7 series.
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As shown on :ref:`line 9 <makefile-example>` of the example Makefile, you will also need to define the specific FPGA part
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number for your chip. To do this, you need to add the following line of code to your Makefile
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depending on your hardware:
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.. tabs::
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.. group-tab:: Arty_35T
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.. code-block:: bash
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:name: example-part-a35t-group
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PARTNAME := xc7a35tcsg324-1
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.. group-tab:: Arty_100T
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.. code-block:: bash
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:name: example-part-a100t-group
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PARTNAME := xc7a100tcsg324-1
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.. group-tab:: Nexus 4 DDR
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.. code-block:: bash
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:name: example-part-nexys4ddr-group
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PARTNAME := xc7a100tcsg324-1
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.. group-tab:: Basys3
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.. code-block:: bash
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:name: example-part-basys3-group
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PARTNAME := xc7a35tcpg236-1
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.. group-tab:: Zybo Z7
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.. code-block:: bash
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:name: example-part-zybo-group
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PARTNAME := xc7z010clg400-1
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.. group-tab:: Nexys Video
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.. code-block:: bash
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:name: example-part-nexys_video-group
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PARTNAME := xc7a200tsbg484-1
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Constraint files
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----------------
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:ref:`Line 10 <makefile-example>` shows how you can specify what constraint files are being used for your design. The
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general syntax depends on whether you are using XDC files or a SDC+PCF pair:
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:ref:`Lines 7-9 <makefile-example>` show how you can specify what constraint files are being used for
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your design. The general syntax depends on whether you are using XDC files or a SDC+PCF pair:
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.. tabs::
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|
@ -248,52 +98,13 @@ general syntax depends on whether you are using XDC files or a SDC+PCF pair:
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PCF := ${current_dir}/<name of PCF file>
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SDC := ${current_dir}/<name of SDC file>
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Note that the :ref:`lines 22, 25, 28, and 31 <makefile-example>` (.eblif, net, place, and route) will also need to change
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depending on if you use an XDC file or some combination of SDC and PCF files. The following
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snippets show the differences and the areas that will need to change:
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.. tabs::
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.. note::
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.. group-tab:: XDC
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:ref:`Line 1 <makefile-example>` calls a make function ``CURDIR`` which returns the absolute
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path for the current directory. :ref:`Line 9 <makefile-example>` simply includes the path to the
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common makefile.
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.. code-block:: bash
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:lineno-start: 21
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:emphasize-lines: 2
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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.. group-tab:: SDC+PCF
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.. code-block:: bash
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:lineno-start: 21
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:emphasize-lines: 5, 8, 11
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC}
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
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|
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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||||
|
||||
|
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|
||||
:ref:`Lines 33-37 <makefile-example>` (running ``symbiflow_write_fasm`` and ``symbiflow_write_bitstream``) typically do
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not change within the Makefile from design to design.
|
||||
|
||||
A Note on the example designs use of ifeq/else ifeq blocks
|
||||
-------------------------------------------------------------
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||||
|
@ -305,60 +116,42 @@ is from lines 9-39 of `the Makefile from counter test <https://github.com/SymbiF
|
|||
|
||||
.. code-block:: bash
|
||||
:name: counter-test Makefile snippet
|
||||
:lineno-start: 9
|
||||
:lineno-start: 5
|
||||
|
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ifeq ($(TARGET),arty_35)
|
||||
PARTNAME := xc7a35tcsg324-1
|
||||
XDC:=${current_dir}/arty.xdc
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
|
||||
XDC := ${current_dir}/arty.xdc
|
||||
else ifeq ($(TARGET),arty_100)
|
||||
PARTNAME := xc7a100tcsg324-1
|
||||
XDC:=${current_dir}/arty.xdc
|
||||
DEVICE := xc7a100t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
|
||||
XDC := ${current_dir}/arty.xdc
|
||||
else ifeq ($(TARGET),nexys4ddr)
|
||||
PARTNAME:= xc7a100tcsg324-1
|
||||
XDC:=${current_dir}/nexys4ddr.xdc
|
||||
DEVICE := xc7a100t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
|
||||
XDC := ${current_dir}/nexys4ddr.xdc
|
||||
else ifeq ($(TARGET),zybo)
|
||||
PARTNAME := xc7z010clg400-1
|
||||
XDC := ${current_dir}/zybo.xdc
|
||||
DEVICE := xc7z010_test
|
||||
BITSTREAM_DEVICE := zynq7
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/zybo
|
||||
VERILOG := ${current_dir}/counter_zynq.v
|
||||
XDC := ${current_dir}/zybo.xdc
|
||||
SOURCES:=${current_dir}/counter_zynq.v
|
||||
else ifeq ($(TARGET),nexys_video)
|
||||
PARTNAME := xc7a200tsbg484-1
|
||||
XDC := ${current_dir}/nexys_video.xdc
|
||||
DEVICE := xc7a200t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/nexys_video
|
||||
XDC := ${current_dir}/nexys_video.xdc
|
||||
else
|
||||
PARTNAME := xc7a35tcpg236-1
|
||||
XDC := ${current_dir}/basys3.xdc
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/basys3
|
||||
XDC := ${current_dir}/basys3.xdc
|
||||
endif
|
||||
|
||||
This snippet of code is an if else block used to set the specific PARTNAME and DEVICE parameters
|
||||
for different types of hardware. Since each FPGA has a unique pin configuration, the block also
|
||||
defines a constraint file specific to the hardware being used (i.e. ``basys3.xdc``,
|
||||
This snippet of code is an if else block used to set device specific constraints (i.e. ``basys3.xdc``,
|
||||
``nexys_video.xdc``). The code block determines what type of hardware is being used based upon a
|
||||
TARGET variable which is assumed to be defined before running make. For example, you may recall
|
||||
running ``TARGET="<board type>" make -C counter_test`` before building the counter test example.
|
||||
This command sets the TARGET variable to the type of hardware you are using.
|
||||
|
||||
The if else block is completely optional. If you are only using one type of hardware for your
|
||||
designs, then you could just use something similar to :ref:`lines 5, 9 and 10 <makefile-example>` in our example:
|
||||
designs you could just specify the TARGET variable within your makefile like so:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: device-partname-snippet
|
||||
:emphasize-lines: 2
|
||||
:linenos:
|
||||
|
||||
DEVICE := xc7a50t_test
|
||||
current_dir := ${CURDIR}
|
||||
TARGET := basys3
|
||||
TOP := ${current_dir}/# put the name of your top module here
|
||||
SOURCES := ${current_dir}/# put your HDL sources here
|
||||
...
|
||||
|
||||
PARTNAME := xc7a35tcpg236-1
|
||||
XDC := ${current_dir}/<name of XDC file>
|
||||
|
||||
If you plan on using multiple types of hardware for your designs, then it might be better to just
|
||||
copy the if else block from one of the Symbiflow-examples. Note that you may need to change the
|
||||
names for the XDC or PCF+SDC parameters to match the names you have used. Also remember that you
|
||||
will need to set the TARGET variable before running make on your design.
|
||||
By setting the ``TARGET`` variable within the Makefile itself, you don't even have to specify
|
||||
the TARGET variable before calling make. You can just use ``make -C <path to directory containing
|
||||
your design>``
|
||||
|
|
|
@ -1,66 +0,0 @@
|
|||
# This Makefile can be add to your design to compile projects using Verilog as an HDL,
|
||||
# and an XDC as a constraint. You can also make changes to this file to build more specialized designs.
|
||||
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
|
||||
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
|
||||
TOP := top
|
||||
VERILOG := ${current_dir}/*.v
|
||||
DEVICE := xc7a50t_test
|
||||
BITSTREAM_DEVICE := artix7
|
||||
BUILDDIR := build
|
||||
|
||||
ifeq ($(TARGET),arty_35)
|
||||
PARTNAME := xc7a35tcsg324-1
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
|
||||
else ifeq ($(TARGET),arty_100)
|
||||
PARTNAME := xc7a100tcsg324-1
|
||||
DEVICE := xc7a100t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
|
||||
else ifeq ($(TARGET),nexys4ddr)
|
||||
PARTNAME := xc7a100tcsg324-1
|
||||
DEVICE := xc7a100t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
|
||||
else ifeq ($(TARGET),zybo)
|
||||
PARTNAME := xc7z010clg400-1
|
||||
DEVICE := xc7z010_test
|
||||
BITSTREAM_DEVICE := zynq7
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/zybo
|
||||
VERILOG := ${current_dir}/*.v
|
||||
else ifeq ($(TARGET),nexys_video)
|
||||
PARTNAME := xc7a200tsbg484-1
|
||||
DEVICE := xc7a200t_test
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/nexys_video
|
||||
else
|
||||
PARTNAME := xc7a35tcpg236-1
|
||||
BOARD_BUILDDIR := ${BUILDDIR}/basys3
|
||||
endif
|
||||
|
||||
XDC:=${current_dir}/*.xdc
|
||||
|
||||
.DELETE_ON_ERROR:
|
||||
|
||||
|
||||
all: ${BOARD_BUILDDIR}/${TOP}.bit
|
||||
|
||||
${BOARD_BUILDDIR}:
|
||||
mkdir -p ${BOARD_BUILDDIR}
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}
|
||||
|
||||
${BOARD_BUILDDIR}/${TOP}.bit: ${BOARD_BUILDDIR}/${TOP}.fasm
|
||||
cd ${BOARD_BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
|
||||
|
||||
clean:
|
||||
rm -rf ${BUILDDIR}
|
|
@ -45,11 +45,9 @@ toolchain will automatically generate one to provide clock constraints to VTR.
|
|||
Makefile
|
||||
+++++++++
|
||||
|
||||
If you have used verilog as your HDL and an XDC as your constraint, you can add this
|
||||
:download:`Makefile <master_makefile/Makefile>` to your design directory instead of building your
|
||||
own. If you have used a different HDL than verilog or have used a combination of PCF+SDC
|
||||
constraint files, you can find instructions for how to modify the provided makefile or create
|
||||
your own in the `Customizing Makefiles <customizing-makefiles.html>`_ page.
|
||||
Visit the `Customizing Makefiles <customizing-makefiles.html>`_ page to learn how to make a simple
|
||||
Makefile for your designs. After following the directions listed there return to this page to
|
||||
finish building your custom design.
|
||||
|
||||
Building your personal projects
|
||||
-------------------------------
|
||||
|
@ -93,6 +91,21 @@ Then, depending on your board type run:
|
|||
:name: example-counter-basys3-group
|
||||
|
||||
TARGET="basys3" make -C .
|
||||
|
||||
.. group-tab:: Nexys Video
|
||||
|
||||
.. code-block:: bash
|
||||
:name: example-counter-nexys_video-group
|
||||
|
||||
TARGET="nexys_video" make -C counter_test
|
||||
|
||||
.. group-tab:: Zybo Z7
|
||||
|
||||
.. code-block:: bash
|
||||
:name: example-counter-zybo-group
|
||||
|
||||
TARGET="zybo" make -C counter_test
|
||||
|
||||
|
||||
If your design builds without error, the bitstream can be found in the following location:
|
||||
|
||||
|
@ -101,7 +114,8 @@ If your design builds without error, the bitstream can be found in the following
|
|||
cd build/<board>
|
||||
|
||||
Once you navigate to the directory containing the bitstream, use the following commands on the
|
||||
**Arty and Basys3** to upload the design to your board:
|
||||
**Arty and Basys3** to upload the design to your board. Make sure to change ``top.bit`` to the
|
||||
name you used for your top level module:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
|
|
@ -170,6 +170,18 @@ Notice that the specification for the part number is a lowercase ``-p`` instead
|
|||
``-P`` as in the placement step. Also note that the ``-d`` in write_bitstream defines the FPGA
|
||||
family instead of the fabric as in the write_fasm step.
|
||||
|
||||
.. warning::
|
||||
|
||||
If you change the name of the output for your bitstream to something other than top.bit then the
|
||||
openocd command used in the examples would need to change too. For example if I used
|
||||
``-b my_module_top`` in symbiflow_write_bitstream then my openocd command would change to:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 my_module_top.bit; exit"
|
||||
|
||||
Note that the only part of the command that changes is "<top module name>.bit;"
|
||||
|
||||
The following example generates a bitstream file named example.bit for the basys3 board:
|
||||
|
||||
.. code-block:: bash
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/top.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/*.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/*.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/*.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ TOP := top
|
|||
SOURCES := ${proj_f_dir}/*.sv
|
||||
XDC := ${proj_f_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../../../common/Makefile
|
||||
include ${current_dir}/../../../../common/common.mk
|
||||
|
|
|
@ -5,4 +5,4 @@ SOURCES := ${current_dir}/*.sv
|
|||
|
||||
XDC := ${current_dir}/basys3.xdc
|
||||
|
||||
include ${current_dir}/../../../common/Makefile
|
||||
include ${current_dir}/../../../common/common.mk
|
||||
|
|
|
@ -17,5 +17,5 @@ else
|
|||
XDC := ${current_dir}/basys3.xdc
|
||||
endif
|
||||
|
||||
include ${current_dir}/../../common/Makefile
|
||||
include ${current_dir}/../../common/common.mk
|
||||
|
||||
|
|
|
@ -43,13 +43,13 @@ At completion, the bitstreams are located in the build directory:
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
cd counter_test/build/<board>
|
||||
counter_test/build/<board>
|
||||
|
||||
Now, for **Arty and Basys3**, you can upload the design with:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
|
||||
TARGET="<board type>" make download -C counter_test
|
||||
|
||||
|
||||
The result should be as follows:
|
||||
|
|
|
@ -7,4 +7,4 @@ PCF := ${current_dir}/arty.pcf
|
|||
SDC := ${current_dir}/arty.sdc
|
||||
XDC := ${current_dir}/arty.xdc
|
||||
|
||||
include ${current_dir}/../../common/Makefile
|
||||
include ${current_dir}/../../common/common.mk
|
|
@ -22,13 +22,13 @@ At completion, the bitstreams are located in the build directory:
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
cd linux_litex_demo/build/<board>
|
||||
linux_litex_demo/build/<board>
|
||||
|
||||
Now you can upload the design with:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
|
||||
TARGET="<board type>" make download -C linux_litex_demo
|
||||
|
||||
.. note::
|
||||
|
||||
|
|
|
@ -21,4 +21,4 @@ else
|
|||
PCF := ${current_dir}/basys3.pcf
|
||||
endif
|
||||
|
||||
include ${current_dir}/../../common/Makefile
|
||||
include ${current_dir}/../../common/common.mk
|
|
@ -36,7 +36,7 @@ Now you can upload the design with:
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
|
||||
TARGET="<board type>" make download -C picosoc_demo
|
||||
|
||||
|
||||
You should observe the following line in the OpenOCD output:
|
||||
|
|
|
@ -6,4 +6,4 @@ SOURCES += ${current_dir}/pulse_led.v
|
|||
|
||||
XDC := ${current_dir}/arty_35.xdc
|
||||
|
||||
include ${current_dir}/../../common/Makefile
|
||||
include ${current_dir}/../../common/common.mk
|
|
@ -16,13 +16,13 @@ At completion, the bitstreams are located in the build directory:
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
cd pulse_width_led/build/arty_35
|
||||
pulse_width_led/build/arty_35
|
||||
|
||||
Now, you can upload the design with:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
|
||||
TARGET="arty_35" make download -C pulse_width_led
|
||||
|
||||
After downloading the bitstream, you can experiment with and mix different amounts of red, green, and
|
||||
blue on RGB led 0 by toggling different switches and buttons on and off. From left to right:
|
||||
|
|
|
@ -5,4 +5,4 @@ SOURCES := ${current_dir}/*.sv
|
|||
|
||||
XDC := ${current_dir}/basys3.xdc
|
||||
|
||||
include ${current_dir}/../../common/Makefile
|
||||
include ${current_dir}/../../common/common.mk
|
|
@ -15,13 +15,13 @@ At completion, the bitstream is located in the build directory:
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
cd timer/build/basys3
|
||||
timer/build/basys3
|
||||
|
||||
Now, you can upload the design with:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
|
||||
TARGET="basys3" make download -C timer
|
||||
|
||||
After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
|
||||
Press the center button to reset the counter. The following gives a visual example:
|
||||
|
|
Loading…
Reference in New Issue