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Merge pull request #178 from WhiteNinjaZ/doc-update 

Makefile Doc update
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common/Makefile → common/common.mk
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329
docs/customizing-makefiles.rst
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@ -2,121 +2,73 @@ Customizing the Makefiles
==========================
A powerful tool in creating your own designs is understanding how to generate your own Makefile to
compile projects. This tutorial walks you through some of the key aspects of working with Makefiles
and explains how you can create Makefiles for your own designs.
compile projects. This tutorial walks you through how to do that.
If you would like to use methods other than a Makefile to build and compile your designs
(such as python or bash scripts) or if you would like to learn more about the various Symbiflow
commands used by the Makefile to build and compile designs take a look at the
commands used by the common Makefile to build and compile designs take a look at the
`Understanding Toolchain Commands <understanding-commands.html>`_ page.
Example
-------
Every example design in Symbiflow has its own Makefile. For example
`counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_,
`Linux Litex demo <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/linux_litex_demo/Makefile>`_,
and `PicoSoC demo <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/picosoc_demo/Makefile>`_
all have there own unique Makefiles for compiling and building respective designs. To understand
how to set up a Makefile in Symbiflow, lets take a look at a simple Makefile. The following code
is based on the Makefile within `counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_
and has been modified slightly for simplicity. Highlighted lines within the code below are of
particular interest and will change depending on your specific design elements and hardware.
Lines that are not highlighted do not change from design to design and can be copy and pasted
into your own Makefile.
By including Symbiflow's provided common Makefile in your designs, running the commands necessary for building
your personal projects is incredibly simple. All you have to do is run a few simple commands and set
a few variables.
Create a makefile for your project by running ``touch Makefile``, and add the following to the contents.
.. code-block:: bash
:name: makefile-example
:emphasize-lines: 3, 4, 5, 6, 9, 10, 22, 25, 28, 31
:linenos:
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP := top
VERILOG := ${current_dir}/counter.v
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
BUILDDIR := build
current_dir := ${CURDIR}
TOP := <put the name of your top module here>
SOURCES := ${current_dir}/<put your HDL sources here>
# Include your constraint file path(s) below. Use either an XDC file
# or a PCF+SDC pair. Don't use all three file types.
XDC := ${current_dir}/<name of your pcf file if applicable>
PCF := ${current_dir}/<name of your xdc file if applicable>
SDC := ${current_dir}/<name of your sdc file if applicable>
PARTNAME := xc7a35tcpg236-1
XDC := ${current_dir}/basys3.xdc
BOARD_BUILDDIR := ${BUILDDIR}/basys3
include <path to symbiflow-examples root directory>/common/common.mk
Lets talk briefly about each of the commands in the above makefile
.DELETE_ON_ERROR:
Adding HDL Sources and Specifying the Top Module
------------------------------------------------
all: ${BOARD_BUILDDIR}/${TOP}.bit
:ref:`Line 2<makefile-example>` in the Makefile shows how to define the name for your top level module.
For example, if your top module was named ``module switches ( ...`` then you would simply uncomment
line 3 and change the text in ``<>`` to ``TOP := switches``.
${BOARD_BUILDDIR}:
mkdir -p ${BOARD_BUILDDIR}
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
cd ${BOARD_BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}
${BOARD_BUILDDIR}/${TOP}.bit: ${BOARD_BUILDDIR}/${TOP}.fasm
cd ${BOARD_BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
clean:
rm -rf ${BUILDDIR}
Adding HDL files to your design
--------------------------------
:ref:`Line 3 <makefile-example>` in the Makefile shows how to define the name for your top level module. For example, if
your top module was named ``module switches ( ...`` then you would simply change line 3 to
``TOP := switches``.
.. warning::
If you change the name of your top level module then the command you use to download the bitstream to
your board using ``openocd`` will need to change slightly from what is provided in the examples. For
instance, if you changed the top level module name to ``TOP := my_module_top`` then the openocd command
would change to:
.. code-block:: bash
openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 my_module_top.bit; exit"
Note that the only part of the command that changes is "<top module name>.bit;"
:ref:`Line 4 <makefile-example>` in the Makefile shows how to add HDL files to the design. The general syntax is:
``<HDL language>:=${current_dir}/<your HDL file path>``. You can also add multiple HDL files to a
:ref:`Line 3<makefile-example>` in the Makefile shows how to add HDL files to the design. The general
syntax is: ``SOURCES:=${current_dir}/<your HDL file path>``. You can also add multiple HDL files to a
design using the following syntax:
.. code-block:: bash
:name: multi-file-example
<HDL language> := ${current_dir}/<HDL file 1> \
${current_dir}/<HDL file 2> \
${current_dir}/<HDL file 3> \
${current_dir}/<HDL file 4> \
...
SOURCES := ${current_dir}/<HDL file 1> \
${current_dir}/<HDL file 2> \
${current_dir}/<HDL file 3> \
...
${current_dir}/<HDL file n> \
You could also use wildcards to collect all HDL file types of a specific extension and add them
to your design. For example, if you wanted to add all verilog files within the current directory
to your design, you could replace line 4 in the Makefile with:
to your design, you could replace line 3 in the Makefile with:
.. code-block:: bash
:name: wildcard-example
VERILOG := ${current_dir}/*.v
SOURCES := ${current_dir}/*.v
To include SystemVerilog HDL in your designs simply change the ``.v`` extension in the examples
above to a ``.sv``. You might also want to change the ``VERILOG`` bash variables throughout the
Makefile to ``SYSTEM_VERILOG`` to improve readability.
above to a ``.sv``.
.. note::
@ -124,114 +76,12 @@ Makefile to ``SYSTEM_VERILOG`` to improve readability.
SystemVerilog can also be run through the toolchain but more complicated
designs may not be fully supported.
Setting the Board Type and Part Name
-------------------------------------
:ref:`Line 5 <makefile-example>` in the example Makefile defines the device fabric
for the board being used in the project. Several different device fabrics are
supported and a listing of the commands for each follow:
.. tabs::
.. group-tab:: Arty_35T
.. code-block:: bash
:name: example-counter-a35t-group
DEVICE := xc7a50t_test
.. group-tab:: Arty_100T
.. code-block:: bash
:name: example-counter-a100t-group
DEVICE := xc7a100t_test
.. group-tab:: Nexus 4 DDR
.. code-block:: bash
:name: example-counter-nexys4ddr-group
DEVICE := xc7a100t_test
.. group-tab:: Basys3
.. code-block:: bash
:name: example-counter-basys3-group
DEVICE := xc7a50t_test
.. group-tab:: Zybo Z7
.. code-block:: bash
:name: example-counter-zybo-group
DEVICE := xc7z010_test
.. group-tab:: Nexys Video
.. code-block:: bash
:name: example-counter-nexys_video-group
DEVICE := xc7a200t_test
:ref:`Line 7 <makefile-example>` defines the family for your FPGA. For example basys3 and arty boards are from the artix7
family while zybo boards are from the zynq7 series.
As shown on :ref:`line 9 <makefile-example>` of the example Makefile, you will also need to define the specific FPGA part
number for your chip. To do this, you need to add the following line of code to your Makefile
depending on your hardware:
.. tabs::
.. group-tab:: Arty_35T
.. code-block:: bash
:name: example-part-a35t-group
PARTNAME := xc7a35tcsg324-1
.. group-tab:: Arty_100T
.. code-block:: bash
:name: example-part-a100t-group
PARTNAME := xc7a100tcsg324-1
.. group-tab:: Nexus 4 DDR
.. code-block:: bash
:name: example-part-nexys4ddr-group
PARTNAME := xc7a100tcsg324-1
.. group-tab:: Basys3
.. code-block:: bash
:name: example-part-basys3-group
PARTNAME := xc7a35tcpg236-1
.. group-tab:: Zybo Z7
.. code-block:: bash
:name: example-part-zybo-group
PARTNAME := xc7z010clg400-1
.. group-tab:: Nexys Video
.. code-block:: bash
:name: example-part-nexys_video-group
PARTNAME := xc7a200tsbg484-1
Constraint files
----------------
:ref:`Line 10 <makefile-example>` shows how you can specify what constraint files are being used for your design. The
general syntax depends on whether you are using XDC files or a SDC+PCF pair:
:ref:`Lines 7-9 <makefile-example>` show how you can specify what constraint files are being used for
your design. The general syntax depends on whether you are using XDC files or a SDC+PCF pair:
.. tabs::
@ -248,52 +98,13 @@ general syntax depends on whether you are using XDC files or a SDC+PCF pair:
PCF := ${current_dir}/<name of PCF file>
SDC := ${current_dir}/<name of SDC file>
Note that the :ref:`lines 22, 25, 28, and 31 <makefile-example>` (.eblif, net, place, and route) will also need to change
depending on if you use an XDC file or some combination of SDC and PCF files. The following
snippets show the differences and the areas that will need to change:
.. tabs::
.. note::
.. group-tab:: XDC
:ref:`Line 1 <makefile-example>` calls a make function ``CURDIR`` which returns the absolute
path for the current directory. :ref:`Line 9 <makefile-example>` simply includes the path to the
common makefile.
.. code-block:: bash
:lineno-start: 21
:emphasize-lines: 2
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
.. group-tab:: SDC+PCF
.. code-block:: bash
:lineno-start: 21
:emphasize-lines: 5, 8, 11
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC}
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
:ref:`Lines 33-37 <makefile-example>` (running ``symbiflow_write_fasm`` and ``symbiflow_write_bitstream``) typically do
not change within the Makefile from design to design.
A Note on the example designs use of ifeq/else ifeq blocks
-------------------------------------------------------------
@ -305,60 +116,42 @@ is from lines 9-39 of `the Makefile from counter test <https://github.com/SymbiF
.. code-block:: bash
:name: counter-test Makefile snippet
:lineno-start: 9
:lineno-start: 5
ifeq ($(TARGET),arty_35)
PARTNAME := xc7a35tcsg324-1
XDC:=${current_dir}/arty.xdc
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
XDC := ${current_dir}/arty.xdc
else ifeq ($(TARGET),arty_100)
PARTNAME := xc7a100tcsg324-1
XDC:=${current_dir}/arty.xdc
DEVICE := xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
XDC := ${current_dir}/arty.xdc
else ifeq ($(TARGET),nexys4ddr)
PARTNAME:= xc7a100tcsg324-1
XDC:=${current_dir}/nexys4ddr.xdc
DEVICE := xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
XDC := ${current_dir}/nexys4ddr.xdc
else ifeq ($(TARGET),zybo)
PARTNAME := xc7z010clg400-1
XDC := ${current_dir}/zybo.xdc
DEVICE := xc7z010_test
BITSTREAM_DEVICE := zynq7
BOARD_BUILDDIR := ${BUILDDIR}/zybo
VERILOG := ${current_dir}/counter_zynq.v
XDC := ${current_dir}/zybo.xdc
SOURCES:=${current_dir}/counter_zynq.v
else ifeq ($(TARGET),nexys_video)
PARTNAME := xc7a200tsbg484-1
XDC := ${current_dir}/nexys_video.xdc
DEVICE := xc7a200t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys_video
XDC := ${current_dir}/nexys_video.xdc
else
PARTNAME := xc7a35tcpg236-1
XDC := ${current_dir}/basys3.xdc
BOARD_BUILDDIR := ${BUILDDIR}/basys3
XDC := ${current_dir}/basys3.xdc
endif
This snippet of code is an if else block used to set the specific PARTNAME and DEVICE parameters
for different types of hardware. Since each FPGA has a unique pin configuration, the block also
defines a constraint file specific to the hardware being used (i.e. ``basys3.xdc``,
This snippet of code is an if else block used to set device specific constraints (i.e. ``basys3.xdc``,
``nexys_video.xdc``). The code block determines what type of hardware is being used based upon a
TARGET variable which is assumed to be defined before running make. For example, you may recall
running ``TARGET="<board type>" make -C counter_test`` before building the counter test example.
This command sets the TARGET variable to the type of hardware you are using.
The if else block is completely optional. If you are only using one type of hardware for your
designs, then you could just use something similar to :ref:`lines 5, 9 and 10 <makefile-example>` in our example:
designs you could just specify the TARGET variable within your makefile like so:
.. code-block:: bash
:name: device-partname-snippet
:emphasize-lines: 2
:linenos:
DEVICE := xc7a50t_test
current_dir := ${CURDIR}
TARGET := basys3
TOP := ${current_dir}/# put the name of your top module here
SOURCES := ${current_dir}/# put your HDL sources here
...
PARTNAME := xc7a35tcpg236-1
XDC := ${current_dir}/<name of XDC file>
If you plan on using multiple types of hardware for your designs, then it might be better to just
copy the if else block from one of the Symbiflow-examples. Note that you may need to change the
names for the XDC or PCF+SDC parameters to match the names you have used. Also remember that you
will need to set the TARGET variable before running make on your design.
By setting the ``TARGET`` variable within the Makefile itself, you don't even have to specify
the TARGET variable before calling make. You can just use ``make -C <path to directory containing
your design>``

66
docs/master_makefile/Makefile
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@ -1,66 +0,0 @@
# This Makefile can be add to your design to compile projects using Verilog as an HDL,
# and an XDC as a constraint. You can also make changes to this file to build more specialized designs.
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP := top
VERILOG := ${current_dir}/*.v
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
BUILDDIR := build
ifeq ($(TARGET),arty_35)
PARTNAME := xc7a35tcsg324-1
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
else ifeq ($(TARGET),arty_100)
PARTNAME := xc7a100tcsg324-1
DEVICE := xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
else ifeq ($(TARGET),nexys4ddr)
PARTNAME := xc7a100tcsg324-1
DEVICE := xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
else ifeq ($(TARGET),zybo)
PARTNAME := xc7z010clg400-1
DEVICE := xc7z010_test
BITSTREAM_DEVICE := zynq7
BOARD_BUILDDIR := ${BUILDDIR}/zybo
VERILOG := ${current_dir}/*.v
else ifeq ($(TARGET),nexys_video)
PARTNAME := xc7a200tsbg484-1
DEVICE := xc7a200t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys_video
else
PARTNAME := xc7a35tcpg236-1
BOARD_BUILDDIR := ${BUILDDIR}/basys3
endif
XDC:=${current_dir}/*.xdc
.DELETE_ON_ERROR:
all: ${BOARD_BUILDDIR}/${TOP}.bit
${BOARD_BUILDDIR}:
mkdir -p ${BOARD_BUILDDIR}
${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
cd ${BOARD_BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}
${BOARD_BUILDDIR}/${TOP}.bit: ${BOARD_BUILDDIR}/${TOP}.fasm
cd ${BOARD_BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
clean:
rm -rf ${BUILDDIR}

26
docs/personal-designs.rst
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@ -45,11 +45,9 @@ toolchain will automatically generate one to provide clock constraints to VTR.
Makefile
+++++++++
If you have used verilog as your HDL and an XDC as your constraint, you can add this
:download:`Makefile <master_makefile/Makefile>` to your design directory instead of building your
own. If you have used a different HDL than verilog or have used a combination of PCF+SDC
constraint files, you can find instructions for how to modify the provided makefile or create
your own in the `Customizing Makefiles <customizing-makefiles.html>`_ page.
Visit the `Customizing Makefiles <customizing-makefiles.html>`_ page to learn how to make a simple
Makefile for your designs. After following the directions listed there return to this page to
finish building your custom design.
Building your personal projects
-------------------------------
@ -93,6 +91,21 @@ Then, depending on your board type run:
:name: example-counter-basys3-group
TARGET="basys3" make -C .
.. group-tab:: Nexys Video
.. code-block:: bash
:name: example-counter-nexys_video-group
TARGET="nexys_video" make -C counter_test
.. group-tab:: Zybo Z7
.. code-block:: bash
:name: example-counter-zybo-group
TARGET="zybo" make -C counter_test
If your design builds without error, the bitstream can be found in the following location:
@ -101,7 +114,8 @@ If your design builds without error, the bitstream can be found in the following
cd build/<board>
Once you navigate to the directory containing the bitstream, use the following commands on the
**Arty and Basys3** to upload the design to your board:
**Arty and Basys3** to upload the design to your board. Make sure to change ``top.bit`` to the
name you used for your top level module:
.. code-block:: bash

12
docs/understanding-commands.rst
View File

@ -170,6 +170,18 @@ Notice that the specification for the part number is a lowercase ``-p`` instead
``-P`` as in the placement step. Also note that the ``-d`` in write_bitstream defines the FPGA
family instead of the fabric as in the write_fasm step.
.. warning::
If you change the name of the output for your bitstream to something other than top.bit then the
openocd command used in the examples would need to change too. For example if I used
``-b my_module_top`` in symbiflow_write_bitstream then my openocd command would change to:
.. code-block:: bash
openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 my_module_top.bit; exit"
Note that the only part of the command that changes is "<top module name>.bit;"
The following example generates a bitstream file named example.bit for the basys3 board:
.. code-block:: bash

2
projf-makefiles/hello/hello-arty/A/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/B/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/C/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/D/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/E/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/F/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/G/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/H/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/top.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/I/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/*.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/J/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/*.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/K/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/*.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
projf-makefiles/hello/hello-arty/L/Makefile
View File

@ -5,4 +5,4 @@ TOP := top
SOURCES := ${proj_f_dir}/*.sv
XDC := ${proj_f_dir}/arty.xdc
include ${current_dir}/../../../../common/Makefile
include ${current_dir}/../../../../common/common.mk

2
xc7/additional_examples/button_controller/Makefile
View File

@ -5,4 +5,4 @@ SOURCES := ${current_dir}/*.sv
XDC := ${current_dir}/basys3.xdc
include ${current_dir}/../../../common/Makefile
include ${current_dir}/../../../common/common.mk

2
xc7/counter_test/Makefile
View File

@ -17,5 +17,5 @@ else
XDC := ${current_dir}/basys3.xdc
endif
include ${current_dir}/../../common/Makefile
include ${current_dir}/../../common/common.mk

4
xc7/counter_test/README.rst
View File

@ -43,13 +43,13 @@ At completion, the bitstreams are located in the build directory:
.. code-block:: bash
cd counter_test/build/<board>
counter_test/build/<board>
Now, for **Arty and Basys3**, you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
TARGET="<board type>" make download -C counter_test
The result should be as follows:

2
xc7/linux_litex_demo/Makefile
View File

@ -7,4 +7,4 @@ PCF := ${current_dir}/arty.pcf
SDC := ${current_dir}/arty.sdc
XDC := ${current_dir}/arty.xdc
include ${current_dir}/../../common/Makefile
include ${current_dir}/../../common/common.mk

4
xc7/linux_litex_demo/README.rst
View File

@ -22,13 +22,13 @@ At completion, the bitstreams are located in the build directory:
.. code-block:: bash
cd linux_litex_demo/build/<board>
linux_litex_demo/build/<board>
Now you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
TARGET="<board type>" make download -C linux_litex_demo
.. note::

2
xc7/picosoc_demo/Makefile
View File

@ -21,4 +21,4 @@ else
PCF := ${current_dir}/basys3.pcf
endif
include ${current_dir}/../../common/Makefile
include ${current_dir}/../../common/common.mk

2
xc7/picosoc_demo/README.rst
View File

@ -36,7 +36,7 @@ Now you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
TARGET="<board type>" make download -C picosoc_demo
You should observe the following line in the OpenOCD output:

2
xc7/pulse_width_led/Makefile
View File

@ -6,4 +6,4 @@ SOURCES += ${current_dir}/pulse_led.v
XDC := ${current_dir}/arty_35.xdc
include ${current_dir}/../../common/Makefile
include ${current_dir}/../../common/common.mk

4
xc7/pulse_width_led/README.rst
View File

@ -16,13 +16,13 @@ At completion, the bitstreams are located in the build directory:
.. code-block:: bash
cd pulse_width_led/build/arty_35
pulse_width_led/build/arty_35
Now, you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
TARGET="arty_35" make download -C pulse_width_led
After downloading the bitstream, you can experiment with and mix different amounts of red, green, and
blue on RGB led 0 by toggling different switches and buttons on and off. From left to right:

2
xc7/timer/Makefile
View File

@ -5,4 +5,4 @@ SOURCES := ${current_dir}/*.sv
XDC := ${current_dir}/basys3.xdc
include ${current_dir}/../../common/Makefile
include ${current_dir}/../../common/common.mk

4
xc7/timer/README.rst
View File

@ -15,13 +15,13 @@ At completion, the bitstream is located in the build directory:
.. code-block:: bash
cd timer/build/basys3
timer/build/basys3
Now, you can upload the design with:
.. code-block:: bash
openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
TARGET="basys3" make download -C timer
After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
Press the center button to reset the counter. The following gives a visual example: