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f4pga-examples/xc7/timer
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Joshua Fife 024e478151 Ran PWM and timer through verible formatter and linter 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
2021-08-20 13:11:11 -06:00
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clock.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
display_control.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
modify_count.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
time_counter.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
timer.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00