144 lines
4.9 KiB
ReStructuredText
144 lines
4.9 KiB
ReStructuredText
.. _Building-Custom-Designs:
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Building Custom Designs
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=======================
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This section describes how to compile and download your own designs to an FPGA using only
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the F4PGA toolchain.
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Before building any examples, you will need to first install the toolchain. To do this, follow the steps in :ref:`Getting`.
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After you have downloaded the toolchain, follow the steps in :ref:`Building-Examples` by seting the installation
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directory to match what you set it to earlier, assigning the path and source for your conda environment, and activating
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your env.
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Preparing Your Design
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---------------------
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Building a design in F4PGA requires three parts: the HDL files for your design, a constraints
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file, and a Makefile. For simplicity, all three of these design files should be moved to a single
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directory. The location of the directory does not mater as long as the three design elements are all
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within it.
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HDL Files
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+++++++++
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F4PGA provides full support for Verilog. Some support for SystemVerilog HDL code is also
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provided, although more complicated designs written in SystemVerilog may not build properly under
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Yosys. Use whichever method you prefer, and add your design files to the directory of choice.
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If you are using the provided Makefiles to build your design, the top level module in your HDL
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code should be declared as ``module top (...``. Failure to do so will result in an error from
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symbiflow_synth stating something similar to ``ERROR: Module 'top' not found!`` If you are using
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your own makefiles or commands, you can specify your top level module name using the -t flag in
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``symbiflow_synth``.
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Constraint File
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+++++++++++++++
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The F4PGA toolchain supports both .XDC and .PCF+.SDC formats for constraints.
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You can use XDC to define IOPAD, IOSETTINGS, and clock constraints. SDCs can be used to
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define clock constraints and PCFs can be used to define IOPAD constraints only. Use whichever
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method you prefer and add your constraint file(s) to your design directory.
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Note that if you use an XDC file as your constraint and neglect to include your own SDC, the
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toolchain will automatically generate one to provide clock constraints to VTR.
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Makefile
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++++++++
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Visit the `Customizing Makefiles <customizing-makefiles.html>`_ page to learn how to make a simple
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Makefile for your designs. After following the directions listed there return to this page to
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finish building your custom design.
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Building your personal projects
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-------------------------------
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Before you begin building your design, navigate to the directory where you have stored your
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Makefile, HDL, and constraint files:
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.. code-block:: bash
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:name: your-directory
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cd <path to your directory>
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Then, depending on your board type run:
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.. tabs::
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.. group-tab:: Arty_35T
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.. code-block:: bash
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:name: example-counter-a35t-group
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TARGET="arty_35" make -C .
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.. group-tab:: Arty_100T
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.. code-block:: bash
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:name: example-counter-a100t-group
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TARGET="arty_100" make -C .
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.. group-tab:: Nexus4
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.. code-block:: bash
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:name: example-counter-nexys4ddr-group
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TARGET="nexys4ddr" make -C .
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.. group-tab:: Basys3
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.. code-block:: bash
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:name: example-counter-basys3-group
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TARGET="basys3" make -C .
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.. group-tab:: Nexys Video
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.. code-block:: bash
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:name: example-counter-nexys_video-group
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TARGET="nexys_video" make -C counter_test
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.. group-tab:: Zybo Z7
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.. code-block:: bash
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:name: example-counter-zybo-group
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TARGET="zybo" make -C counter_test
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If your design builds without error, the bitstream can be found in the following location:
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.. code-block:: bash
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cd build/<board>
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Once you navigate to the directory containing the bitstream, use the following commands on the
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**Arty and Basys3** to upload the design to your board. Make sure to change ``top.bit`` to the
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name you used for your top level module:
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.. code-block:: bash
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openocd -f ${F4PGA_INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
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.. tip::
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Many of the commands needed to build a project are run multiple times with little to no
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variation. You might consider adding a few aliases or even a few bash functions to your
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.bashrc file to save yourself some typing or repeated copy/paste. For example, instead of
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using the somewhat cumbersome command used to upload the bitstream to Xilinx 7 series FPGA
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every time, you could just add the following lines to your .bashrc file:
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.. code-block:: bash
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:name: bash-functions
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symbi_bit() {
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#Creates and downloads the bitstream to Xilinx 7 series FPGA:
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openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
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}
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Now whenever you need to download a bitstream to the Xilinx-7 series you can simply type
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``symbi_bit`` into the terminal and hit enter.
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