f4pga-examples/.gitmodules
Alessandro Comodi 6227299763 xc7: lite sata add third party code for VexRiscV and improve docs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-11-30 13:41:25 +01:00

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[submodule "third_party/projf-explore"]
path = third_party/projf-explore
url = https://github.com/projf/projf-explore.git
[submodule "third_party/vexriscv-verilog"]
path = third_party/vexriscv-verilog
url = https://github.com/m-labs/VexRiscv-verilog