f4pga-examples/xc7/counter_test/basys3.pcf

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# basys3 100 MHz CLK
set_io clk W5
set_io tx A18
set_io rx B18
# out[0:15] correspond with LD0-LD15 on the basys3
set_io led[0] U16
set_io led[1] E19
set_io led[2] U19
set_io led[3] V19