38 lines
665 B
Verilog
38 lines
665 B
Verilog
module top (
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input wire clk,
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output wire [3:0] led
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);
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wire [63:0] emio_gpio_o;
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wire [63:0] emio_gpio_t;
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wire [63:0] emio_gpio_i;
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wire clk_bufg;
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BUFG BUFG (
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.I(clk),
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.O(clk_bufg)
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);
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wire en_counter = ~emio_gpio_o[0];
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wire count_direction = ~emio_gpio_o[1];
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reg [31:0] counter = 0;
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always @(posedge clk_bufg) begin
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if (en_counter)
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if (count_direction) counter <= counter + 1;
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else counter <= counter - 1;
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end
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assign led = counter[27:24];
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// The PS7
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(* KEEP, DONT_TOUCH *)
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PS7 PS7 (
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.EMIOGPIOO (emio_gpio_o),
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.EMIOGPIOTN(emio_gpio_t),
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.EMIOGPIOI (emio_gpio_i),
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);
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endmodule
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