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18 lines
No EOL
503 B
Verilog
18 lines
No EOL
503 B
Verilog
module top(
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input wire clk,
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input wire [3:0] sw,
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input wire [3:0] btn,
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output wire pulse_red, pulse_blue, pulse_green
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);
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wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG;
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assign pulse_wideR = {1'b0, sw[3:1], 10'd0};
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assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0};
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assign pulse_wideB = {btn[1:0], 11'd0};
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PWM R0(.clk(clk), .pulse(pulse_red), .width(pulse_wideR));
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PWM B0(.clk(clk), .pulse(pulse_green), .width(pulse_wideB));
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PWM G0(.clk(clk), .pulse(pulse_blue), .width(pulse_wideG));
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endmodule |