f4pga-examples/xc7/counter_test/zybo.xdc

17 lines
558 B
Tcl

# Clock pin
set_property LOC K17 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property LOC M14 [get_ports {led[0]}]
set_property LOC M15 [get_ports {led[1]}]
set_property LOC G14 [get_ports {led[2]}]
set_property LOC D18 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 8.0 [get_ports {clk}]