f4pga-examples/xc7/counter_test/basys3.xdc
Alessandro Comodi 8ae95b0d8d xc7: add zynq counter test
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-12-15 11:39:23 +01:00

16 lines
602 B
Tcl

# Clock pin
set_property PACKAGE_PIN W5 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 10.0 [get_ports {clk}]